Dell PowerEdge C5230 - Manual (Page 81)

Using the System Setup Program 81
Table 2-13. MRC DIMM to Error Code Mapping
Table 2-14. MRC POST Code
Node Channel DIMM Error Code
0
0 0
0xA0
0 0 1
0xA1
0 1 0
0xA2
0 1 1
0xA3
POST Code Nomenclature Major
Code Minor
Code Description
STS_DIMM_DETECT B0h Detect DIMM
population
STS_CLOCK_INIT B1h Set DDR3 frequency
STS_SPD_DATA B2h Gather remaining
SPD data
STS_GLOBAL_EARLY B3h Program registers on
the memory controller
level
STS_RANK_DETECT B4h Evaluate RAS modes
and save rank
information
STS_CHANNEL_EARLY B5h Program registers on
the channel level
STS_JEDEC_INIT B6h Perform the JEDEC
defined initialization
sequence
STS_CHANNEL_TRAINI
NG
B7h Train DDR3 ranks
STS_RD_DQS 01h Read DQ/DQS
training