Cypress CY7C1329H User Manual
Page 6
CY7C1329H
Document #: 38-05673 Rev. *B
Page 6 of 16
Truth Table
[2, 3, 4, 5, 6, 7]
Next Cycle
Add. Used
Add. Used
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC
ADV
WRITE
OE
Unselected
None
None
H
X
X
L
X
L
X
X
X
Unselected
None
None
L
L
X
L
L
X
X
X
X
Unselected
None
None
L
X
H
L
L
X
X
X
X
Unselected
None
None
L
L
X
L
H
L
X
X
X
Unselected
None
None
L
X
H
L
H
L
X
X
X
Begin Read
External
None
X
X
X
H
X
X
X
X
X
Begin Read
External
External
L
H
L
L
L
X
X
X
L
Continue Read
Next
External
L
H
L
L
L
X
X
X
H
Continue Read
Next
External
L
H
L
L
H
L
X
L
X
Continue Read
Next
External
L
H
L
L
H
L
X
H
L
Continue Read
Next
External
L
H
L
L
H
L
X
H
H
Suspend Read
Current
Next
X
X
X
L
H
H
L
H
L
Suspend Read
Current
Suspend Read
Current
Next
X
X
X
L
H
H
L
H
H
Suspend Read
Current
Next
H
X
X
L
X
H
L
H
L
Begin Write
Current
Next
H
X
X
L
X
H
L
H
H
Begin Write
Current
Next
X
X
X
L
H
H
L
L
X
Begin Write
External
Next
H
X
X
L
X
H
L
L
X
Continue Write
Next
Current
X
X
X
L
H
H
H
H
L
Continue Write
Next
Current
X
X
X
L
H
H
H
H
H
Suspend Write
Current
Current
H
X
X
L
X
H
H
H
L
Suspend Write
Current
Current
H
X
X
L
X
H
H
H
H
ZZ “Sleep”
None
Current
X
X
X
L
H
H
H
L
X
Truth Table for Read/Write
[2, 3]
Function
GW
BWE
BW
D
BW
C
BW
B
BW
A
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – DQ
A
H
L
H
H
H
L
Write Byte B – DQ
B
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – DQ
C
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – DQ
D
H
L
L
H
H
H
Notes:
2. X = “Don't Care.” H =Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
A
,BW
B
,BW
C
,BW
D
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BW
A
,BW
B
,BW
C
,BW
D
), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
1
, CE
2
, and CE
3
are available only in the TQFP package.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
[A:D]
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).