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Switching characteristics – Cypress CY62157ESL User Manual

Page 6

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CY62157ESL MoBL

®

Document #: 001-43141 Rev. **

Page 6 of 12

Switching Characteristics

Over the Operating Range

[9]

Parameter

Description

45 ns

Unit

Min

Max

Read Cycle

t

RC

Read Cycle Time

45

ns

t

AA

Address to Data Valid

45

ns

t

OHA

Data Hold from Address Change

10

ns

t

ACE

CE LOW to Data Valid

45

ns

t

DOE

OE LOW to Data Valid

22

ns

t

LZOE

OE LOW to LOW-Z

[10]

5

ns

t

HZOE

OE HIGH to High-Z

[10, 11]

18

ns

t

LZCE

CE LOW to Low-Z

[10]

10

ns

t

HZCE

CE HIGH to High-Z

[10, 11]

18

ns

t

PU

CE LOW to Power Up

0

ns

t

PD

CE HIGH to Power Down

45

ns

t

DBE

BLE/BHE LOW to Data Valid

45

ns

t

LZBE

BLE/BHE LOW to Low-Z

[10, 12]

5

ns

t

HZBE

BLE/BHE HIGH to HIGH-Z

[10, 11]

18

ns

Write Cycle

[13]

t

WC

Write Cycle Time

45

ns

t

SCE

CE LOW to Write End

35

ns

t

AW

Address Setup to Write End

35

ns

t

HA

Address Hold from Write End

0

ns

t

SA

Address Setup to Write Start

0

ns

t

PWE

WE Pulse Width

35

ns

t

BW

BLE/BHE LOW to Write End

35

ns

t

SD

Data Setup to Write End

25

ns

t

HD

Data Hold from Write End

0

ns

t

HZWE

WE LOW to High-Z

[10, 11]

18

ns

t

LZWE

WE HIGH to Low-Z

[10]

10

ns

Notes

9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to

3V, and output loading of the specified I

OL

/I

OH

as shown in the

AC Test Loads and Waveforms on page 4

.

10. At any temperature and voltage condition, t

HZCE

is less than t

LZCE

, t

HZBE

is less than t

LZBE

, t

HZOE

is less than t

LZOE

, and t

HZWE

is less than t

LZWE

for any device.

11. t

HZOE

, t

HZCE

, t

HZBE

, and t

HZWE

transitions are measured when the outputs enter a high-impedance state.

12. If both byte enables are toggled together, this value is 10 ns.
13. The internal write time of the memory is defined by the overlap of WE, CE

= V

IL

, BHE, BLE or both = V

IL

. All signals must be active to initiate a write and any of these

signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

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