Cirrus Logic AN364 - Manual (Page 20)

AN364
20 AN364REV3
4 Design Example
The Cirrus Logic CRD1611-8W reference design is used for the design example. The required operating parameters
for the analytical process are outlined in the table below.
4.1 Flyback Design Steps
Step 1) Select a Value for Boost Output Voltage
The CRD1611-8W is a 230V reference design. Boost output voltage V
BST
is 405V nominal.
Step 2) Select an Appropriate FET
Use Equation 3
to calculate maximum boost output voltage V
BST(max)
. The CS1611 limits the boost output
voltage to +10%. V
BST(max)
is calculated using Equation 27:
Using a 300V zener as a clamp device sets the maximum clamp voltage V
CLAMP
to 315V (+5% tolerance),
leaving 40V of V
Margin
to an 800V FET. Using an analytical approach to partition V
CLAMP
into V
Reflected
and
(V
Reflected
- V
CLAMP
) requires assumptions on the switching details.
It is recommended to choose V
Reflected
to equal 70% of V
CLAMP
. Voltage V
Reflected
is set to 220V, leaving 80V
of overshoot to dissipate as leakage inductance energy. The actual overshoot range is from 65V to 95V,
depending on the clamp zener tolerance. See Equation 28:
Step 3) Determine the Flyback Transformer Turns Ratio
Select a turns ratio for the flyback transformer T1 based on the desired output voltage, V
OUT
, and V
Reflected
.
Output voltage V
OUT
is the maximum LED string forward voltage at full current, plus rectifying diode forward
voltage V
F
. Using Equation 4, calculate turns ratio N:
Step 4) Select the Full Brightness Switching Frequency
At full power, the flyback stage operates in valley-switching mode. The addition of a small transition time T3
results in extending time TT and slightly reducing the design frequency. The frequency reduction has a
negligible effect on the design, but requires that time T1, T2 and TT be correctly calculated at full brightness.
An optimal compromise between transformer size and efficiency is reached at a switching frequency of
~85kHz.
To accommodate valley switching, T3 is set to approximately one-half of the resonant period of the flyback
inductor resonance, taking into account all capacitances associated with the FET drain node. Setting T3 to 1
 s
is an acceptable starting value. Once a system is built and validated, the design can be refined. Using
Equation 5, solve for (T1 + T2):
Parameters Symbol Value
Output Power P
OUT
6.6W
AC Line Input Voltage V
IN
230V
Output Voltage V
OUT
15V
Load Current I
OUT
440mA
Maximum Switching Frequency * F
sw(max)
85kHz
* Increasing F
sw
reduces the size of the magnetics but increases switching losses in the FET.
V
BST max  
405V = 1.1 V 445V =  [Eq. 27]
V
Breakdown
V
BST max  
V
CLAMP
V
M in arg
+ + 445V 315V 40V + + 800V = = = [Eq. 28]
N
V
Reflected
V
OUT
--------------------------
220V
15V 0.4V +
------------------------------ 14.3 = = = [Eq. 29]
T1 T2 +
1
F
sw
-----------
 
  T3
–
1
85kHz
------------------
 
  1s
– 11.76 s = = = [Eq. 30]