Cirrus Logic CS5509 - Manual (Page 16)

CS5509
16 DS125F3
Power Supplies and Grounding
The analog and digital supply pins to the CS5509
are brought out on separate pins to minimize noise
coupling between the analog and digital sections of
the chip. In the digital section of the chip the supply
current flows into the VD+ pin and out of the GND
pin. As a CMOS device, the CS5509 requires that
the supply voltage on the VA+ pin always be more
positive than the voltage on any other pin of the de-
vice. If this requirement is not met, the device can
latch-up or be damaged. In all circumstances the
VA+ voltage must remain more positive than the
VD+ or GND pins; VD+ must remain more posi-
tive than the GND pin.
Figure 9a illustrates the System Connection Dia-
gram for the CS5509. Note that all supply pins are
bypassed with 0.1 µF capacitors and that the VD+
digital supply is derived from the VA+ supply. Fig-
ure 9b illustrates the CS5509 operating from a +5V
analog supply and +3.3V digital supply.
When using separate supplies for VA+ and VD+,
VA+ must be established first. VD+ should never
become more positive than VA+ under any operat-
ing condition. Remember to investigate transient
power-up conditions, when one power supply may
have a faster rise time.