Cirrus Logic AN31 - Manual (Page 7)

measurement is required. Figure 6 illustrates an
example circuit in which the power to the bridge
transducer is switched on only when a
measurement is desired.
The circuit as shown is optimized for a +10 V
analog supply. The circuit can be modified
(optimized) to operate from any analog supply
from 11 V to 6.5 V (assuming the +5 V
regulator needs 1.5 V of input/output
differential) by changing the resistor values
which determine the voltage reference to the
converter and by changing the gain resistors in
the amplifier to compensate for the change in the
bridge output signal. The circuit shown
illustrates a 2 mV/V transducer outputting
20 mV full-scale. A gain of 166 amplifies this to
3.32 V into the A/D. The full-scale of the A/D is
set at 3.33 V by dividing down the excitation
voltage.
In the power arrangement shown, the CS5507
A/D uses about 4 mW. The converter is clocked
from an external gate oscillator clock (162 kHz)
to yield a conversion time of 10 msec. When
power is applied to the bridge, a delay must
occur to allow the signal to settle before a valid
conversion can be performed. Settling time to 16
bits after power is applied to the bridge takes
about 3.3 msec. The microcontroller can use an
internal timer to time about 4 msec. to allow for
the delay or the microcontroller can perform a
dummy conversion in the converter to allow for
settling time. When the dummy conversion is
finished (10 msec. later) the conversion data is
discarded and a second conversion is then
performed to make a valid measurement. After
the second conversion is complete (DRDY falls
the second time) power to the bridge is
deactivated and the conversion word is clocked
out of the converter’s serial port.
Power consumed by the transducer dominates
the power dissipated in the circuit. Average
power consumption in the bridge can be reduced
by a factor of at least fifty (<6 mW) if the bridge
is powered for only 20 msec. for a reading each
second. If even lower off power is desired, the
supply to the LT1013 can also be switched along
with the bridge excitation.
CS5509 Switched-Bridge Low-power
Digitizer with +5 V Excitation
The circuit in Figure 7 is similar to the previous
one, but operates from a single +5 V. The circuit
shows a load cell with 3 mV/V sensitivity. A
2 mV/V transducer can be used if additional gain
is added; or the voltage reference into the
converter can be lowered to 1.67 V with some
minor increase in noise. Average power
consumption in the load cell is only 1.5 mW for
one reading per second.
CS5516/CS5520 Using DC Bridge Excitation
The CS5516 (16-bit) and CS5520 (20-bit) A/D
converters are designed for bridge measurement
applications. They include an instrumentation
amplifier with X25 gain, a PGA (programmable
gain amplifier) with gains of 1, 2, 4, and 8, and
a four bit DAC which can trim out offset up to
±
200% of the full scale signal magnitude. The
input span can be adjusted by changing either
the magnitude of the voltage at the VREF pins
of the converter or by changing the PGA gain.
In the circuit shown in Figure 8, the bridge is
excited with
±
5 volts. Resistors R1, R2, and R3
divide the excitation voltage to give a 2.5 V
reference signal into the VREF pins. The input
span at the AIN pins of the converter is
determined by dividing the voltage at the VREF
pins by the PGA gain and the X25
instrumentation amplifier gain. For example,
with 2.5 V into the VREF pins, and the PGA set
to a gain of 8, the input span at the AIN pins is
2.5/(8 X 25) = 12.5 mV in unipolar mode or
±
12.5 mV in bipolar mode. The converter offers
several calibration features to remove offset and
to calibrate the gain slope. The input span of
Bridge Transducer Digitizer Circuits
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