Applications, 1 operational mode/sample rate range select, Table 1. cs5381 mode control – Cirrus Logic CS5381 User Manual

Page 15: 2 system clocking, 1 master mode, Figure 23. cs5381 master mode clocking

DS563F2

CS5381

3. APPLICATIONS

3.1

Operational Mode/Sample Rate Range Select

The output sample rate, Fs, can be adjusted from 2 kHz to 216 kHz. The CS5381 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to

Table 1

3.2

System Clocking

The device supports operation in either Master Mode, where the left/right and serial clocks are synchronous-
ly generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks.
The device also includes a master clock divider in Master Mode where the master clock will be internally
divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV
pin needs to be disabled, set to logic 0.

3.2.1

Master Mode

In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in

Figure 23

. Refer to

Table 2

for common master clock frequencies.

M1 (Pin 14)

M0 (Pin 13)

MODE

Output Sample Rate (Fs)

Single-Speed Mode

2 kHz - 54 kHz

Double-Speed Mode

50 kHz - 108 kHz

Quad-Speed Mode

100 kHz - 216 kHz

Reserved

Table 1. CS5381 Mode Control

ч 128

ч 256

ч 64

LRCK Output

(Equal to Fs)

Single

Speed

Quad

Speed

Double

Speed

ч 2

ч 4

ч 1

SCLK Output

Single

Speed

Quad

Speed

Double

Speed

ч 2

ч 1

MCLK

MDIV

Figure 23. CS5381 Master Mode Clocking