Cirrus Logic CDB43L22 - Manual (Page 4)

4 DS792DB1
CDB43L22
1. SYSTEM OVERVIEW
The CDB43L22 platform provides analog and digital interfaces to the CS43L22 and allows for external DSP and
I²C
® interconnects. On-board power regulators are provided so that an external power supply upto +5 V can be used
to provide power for the digital and analog cores of the CS43L22. On-board peripherals are powered from the USB
connection which also serves as an interface to a PC. The CDB43L22 is configured using Cirrus Logic’s Windows-
compatible FlexGUI software to read/write to device registers.
This section describes the various components on the CDB43L22 and how they are used. Section 2 on page 7 is a
simplified quick connect guide provided for user convenience and can be used to set up the board quickly with the
CS43L22 in its startup default configuration.
Section 3 on page 8 describes the various configuration options in
which the board can be used. Section 4 “Software Mode Control” on page 11 provides further configuration details
and describes software functionality. The CDB43L22 schematic set is shown in Figures 7 through 18 . Section 5 on
page 17 provides a description of all stake headers and connectors, including the default factory settings for all jump-
ers.
1.1 Power
Power is supplied to the evaluation board via the USB connection or by applying +5.0 V to TP2. Jumper J34
allows the user to select the power source. Power (VP) and ground (GND) for the CS43L22 is supplied via
binding posts J35 and J4 (respectively) or by standard AAA batteries in locations BT1, BT2 and BT3. The
voltage provided to the binding posts can be in the range of +2.7 V to +5.25 V. On-board regulators and
jumpers allow the user to connect the CS43L22’s supplies to +1.8 V, 2.5 V or +3.3 V for VL and +1.8 V or
2.5 V for VD, VA and VA_HP. All voltage inputs are referenced to ground using the black binding post J4.
Stake headers J47, J52, J53 and J74 provide a convenient way to measure supply currents to the CS43L22
for VA_HP, VL, VD and VA supplies respectively. The current can be easily calculated by measuring the
voltage drop across the parallel resistors with its associated jumper removed.
NOTE: Stake headers J47, J48, J52, J53 and J74 must be shunted with the supplied jumpers during normal
operation.
WARNING: Please refer to the CS43L22 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS43L22 requires careful attention to power supply and grounding arrangements to optimize perfor-
mance. The CDB43L22 demonstrates these optimal arrangements.
Figure 9 on page 19 provides an over-
view of the connections to the CS43L22. Figure 14 on page 24 shows the component placement, Figure 15
on page 25 shows the top layout, and Figure 18 on page 28 shows the bottom layout. Power supply decou-
pling capacitors are located as close as possible to the CS43L22. Extensive use of ground plane fill helps
reduce radiated noise.
1.3 FPGA
The FPGA controls digital signal routing between the CS43L22, CS8416, SRC, PLL and the I/O stake head-
er. It also provides routing control of the system master clock from an on-board oscillator and the CS8416.
The Cirrus FlexGUI software provides full control of the FPGA’s routing and configuration options.
Section 4
“Software Mode Control” on page 11 provides configuration details.
1.4 CS43L22
A complete description of the CS43L22 can be found in the CS43L22 product data sheet.