Cirrus Logic CDB43L22 - Manual (Page 2)

2 DS792DB1
CDB43L22
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................................. 4
1.1 Power ............................................................................................................................................... 4
1.2 Grounding and Power Supply Decoupling ....................................................................................... 4
1.3 FPGA ............................................................................................................................................... 4
1.4 CS43L22 .......................................................................................................................................... 4
1.5 CS8416 Digital Audio Receiver ........................................................................................................ 5
1.6 Oscillator .......................................................................................................................................... 5
1.7 I/O Stake Headers ........................................................................................................................... 5
1.8 Analog Inputs ................................................................................................................................... 5
1.9 Analog Outputs ................................................................................................................................ 5
1.10 Control Port Connectors ................................................................................................................ 6
1.11 USB Connector .............................................................................................................................. 6
2. QUICK START GUIDE ........................................................................................................................... 7
3. CONFIGURATION OPTIONS ................................................................................................................. 8
3.1 SPDIF In to Headphone or Line Out ................................................................................................ 8
3.2 SPDIF In to Stereo Speaker Out ...................................................................................................... 9
3.3 SPDIF In to Mono Speaker Out ..................................................................................................... 10
4. SOFTWARE MODE CONTROL ........................................................................................................... 11
4.1 Board Configuration Tab ................................................................................................................ 12
4.2 Passthrough, Power and Serial Audio Interface Configuration Tab ............................................... 13
4.3 DSP Engine Tab ............................................................................................................................ 14
4.4 Analog and PWM Output Volume Tab ........................................................................................... 15
4.5 Register Maps Tab ......................................................................................................................... 16
5. SYSTEM CONNECTIONS AND JUMPERS ........................................................................................ 17
6. JUMPER SETTINGS ........................................................................................................................... 18
7. CDB43L22 BLOCK DIAGRAM ............................................................................................................ 19
8. CDB43L22 SCHEMATICS ................................................................................................................... 20
9. CDB43L22 LAYOUT ............................................................................................................................ 24
10. PERFORMANCE PLOTS ................................................................................................................... 29
11. REVISION HISTORY .......................................................................................................................... 31
LIST OF FIGURES
Figure 1.SPDIF In to Headphone or Line Out ............................................................................................. 8
Figure 2.SPDIF In to Stereo Speaker Out ................................................................................................... 9
Figure 3.SPDIF In to Mono Speaker Out .................................................................................................. 10
Figure 4.Board Configuration Tab ............................................................................................................. 12
Figure 5.Passthrough, Power and Serial Audio Interface Configuration Tab ............................................ 13
Figure 6.DSP Engine Tab ......................................................................................................................... 14
Figure 7.Analog and PWM Output Volume Tab ........................................................................................ 15
Figure 8.Register Maps Tab - CS43L22 ................................................................................................... 16
Figure 9.Block Diagram ............................................................................................................................. 19
Figure 10.CS43L22 & Analog I/O (Schematic Sheet 1) ............................................................................ 20
Figure 11.S/PDIF & Digital Interface (Schematic Sheet 2) ....................................................................... 21
Figure 12.Micro & FPGA Control (Schematic Sheet 3) ............................................................................. 22
Figure 13.Power (Schematic Sheet 4) ...................................................................................................... 23
Figure 14.Silk Screen ................................................................................................................................ 24
Figure 15.Top-Side Layer ......................................................................................................................... 25
Figure 16.GND (Layer 2) ........................................................................................................................... 26
Figure 17.Power (Layer 3) ........................................................................................................................ 27
Figure 18.Bottom-Side Layer .................................................................................................................... 28
Figure 19.FFT - S/PDIF Input to HP Output @ -1 dBFS ........................................................................... 29
Figure 20.FFT - S/PDIF Input to HP Output @ -60 dBFS ......................................................................... 29