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Figure 3. external serial mode input timing, Figure 4. internal serial mode input timing, Figure 5. internal serial clock generation – Cirrus Logic CS4361 User Manual

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CS4361

Confidential Draft

9/30/11

sclkh

t

slrs

t

slrd

t

sdlrs

t

sdh

t

sclkl

t

SDATA

SCLK

LRCK

Figure 3. External Serial Mode Input Timing

SDATA

*INTERNAL SCLK

LRCK

sclkw

t

sdlrs

t

sdh

t

sclkr

t

Figure 4. Internal Serial Mode Input Timing

* The SCLK pulses shown are internal to the CS4361.

SDATA

LRCK

MCLK

*INTERNAL SCLK

1

N
2

N

Figure 5. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS4361.

N equals MCLK divided by SCLK

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