Cirrus Logic CS4353 - Manual (Page 14)

14 DS803F3
CS4353
4.2 Sample Rate Range/Operational Mode Detect
The CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when
the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in
Table 2 . Sample rates outside the specified range for each mode are not supported. In addition to a valid
LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device
for speed mode auto-detection; see
Figure 9 .
Table 2. CS4353 Operational Mode Auto-Detect
4.3 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the
MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-
dard audio sample rates and the required MCLK frequency, are illustrated in
Tables 3 - 5 .
Refer to Section 4.4 for the required SCLK timing associated with the selected Digital Interface Format and
to “Switching Specifications - Serial Audio Interface” on page 9 for the maximum allowed clock frequencies.
Table 3. Single-speed Mode Standard Frequencies
Table 4. Double-speed Mode Standard Frequencies
Table 5. Quad-speed Mode Standard Frequencies
Input Sample Rate (Fs) Mode
8 kHz - 54 kHz Single-Speed Mode
84 kHz - 108 kHz Double-Speed Mode
170 kHz - 216 kHz Quad-Speed Mode
Sample Rate
(kHz)
MCLK (MHz)
256x 384x 512x 768x 1024x
32 8.1920 12.2880 16.3840 24.5760 32.7680
44.1 11.2896 16.9344 22.5792 33.8688 45.1584
48 12.2880 18.4320 24.5760 36.8640 49.1520
Sample Rate
(kHz)
MCLK (MHz)
128x 192x 256x 384x 512x
88.2 11.2896 16.9344 22.5792 33.8688 45.1584
96 12.2880 18.4320 24.5760 36.8640 49.1520
Sample Rate
(kHz)
MCLK (MHz)
128x 192x 256x
176.4 22.5792 33.8688 45.1584
192 24.5760 36.8640 49.1520