Cirrus Logic CS4299 - Manual (Page 29)

CS4299
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4.16 PCM Front DAC Rate Register (Index 2Ch)
SR[15:0] Front DAC Sample Rate. The SR[15:0] bits can only be written when the VRA bit of the Extend-
ed Audio Status/Control Register (Index 2Ah) is ‘set’. If the VRA bit is ‘clear’, all writes are ig-
nored and the register reads back BB80h; corresponding to a 48 kHz sample rate. If the VRA
bit is ‘set’, seven standard sample rates are available. If a sample rate written to the register is
not directly supported, the attempted value to be written will be decoded according to the ranges
indicated in Table 7. All register read transactions will reflect the actual value stored (column 2
in Table 7) and not the one attempted to be written.
Default BB80h. This value corresponds to 48 kHz sample rate..
4.17 PCM L/R ADC Rate Register (Index 32h)
SR[15:0] Left/Right ADC Sample Rate. The SR[15:0] bits can only be written when the VRA bit of the
Extended Audio Status/Control Register (Index 2Ah) is ‘set’. If the VRA bit is ‘clear’, all writes
are ignored and the register reads back BB80h; corresponding to a 48 kHz sample rate. If the
VRA bit is ‘set’, seven standard sample rates are available. If a sample rate written to the reg-
ister is not directly supported, the attempted value to be written will be decoded according to
the ranges indicated in Table 7. All register read transactions will reflect the actual value stored
(column 2 in Table 7) and not the one attempted to be written.
Default BB80h. This value corresponds to 48 kHz sample rate.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
Sample rate
(Hz)
SR[15:0]
SR[15:12]
Decode Range
8,000 1F40 0 or 1
11,025 2B11 2
16,000 3E80 3
22,050 5622 4 or 5
32,000 7D00 6 or 7
44,100 AC44 8, 9, or Ah
48,000 BB80 Bh, Ch, Dh, Eh, or Fh
Table 7. Standard Sample Rates
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
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CS4299