IEI Integration PCISA-945GSE v1.01 - Manual (Page 41)

PCISA-945GSE CPU Card
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ƒ Integrated 10/100/1000 transceiver
ƒ Auto-Negotiation with Next Page capability
ƒ Supports PCI Express™ 1.1
ƒ Supports pair swap/polarity/skew correction
ƒ Crossover Detection & & Auto-Correction
ƒ Wake-on-LAN and remote wake-up support
ƒ Microsoft® NDIS5, NDIS6 Checksum Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send and Giant send) support
ƒ Supports Full Duplex flow control (IEEE 802.3x)
ƒ Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
ƒ Supports IEEE 802.1P Layer 2 Priority Encoding
ƒ Supports IEEE 802.1Q VLAN tagging
ƒ Serial EEPROM
ƒ Transmit/Receive on-chip buffer support
ƒ Supports power down/link down power saving
ƒ Supports PCI MSI (Message Signaled Interrupt) and MSI-X
ƒ Supports Receive-Side Scaling (RSS)
2.5.9 SPI Bus Components
The Intel® ICH7M SPI bus is connected to components listed below:
ƒ BIOS chip
2.5.9.1 SPI BIOS
The 4-pin Serial Peripheral Interface (SPI) is connected to an SPI BIOS chip. A licensed
copy of AMI BIOS is preinstalled on the SPI BIOS chip. A master-slave protocol is used for
communication on the SPI bus. The slave is connected to the Intel® ICH7M and is
implemented as a tri-state bus. The SPI BIOS is located on the reverse side of the JSPI1
jumper.