IEI Integration PCIE-Q870-i2 - Manual (Page 41)

PCIE-Q870-i2 PICMG 1.3 CPU Card
Page 24
Pin Description Pin Description
1 GND 2 VCC
3 Output 3 4 Output 2
5 Output 1 6 Output 0
7 Input 3 8 Input 2
9 Input 1 10 Input 0
Table 3-7: Digital I/O Connector Pinouts
3.2.7 EC Debug Connector
CN Label: CN3
CN Type: 18-pin header
CN Location: See Figure 3-8
CN Pinouts: See Table 3-8
The EC debug connector is used for EC debug.
Figure 3-8: EC Debug Connector Location
Pin Description Pin Description
1 EC_EPP_STB# 2 EC_EPP_AFD#
3 EC_EPP_PD0 4 NC
5 EC_EPP_PD1 6 EC_EPP_INIT#
7 EC_EPP_PD2 8 EC_EPP_SLIN#
9 EC_EPP_PD3 10 GND
11 EC_EPP_PD4 12 NC
13 EC_EPP_PD5 14 EC_EPP_BUSY