IEI Integration ROCKY-3786 v4.0 - Manual (Page 24)

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IEI ® Technology, Corp.
electrical interface, and physical package
Software-compatible with thousands of x86 software applications available
MMX-compatible instructions
SSE-compatible instructions
Two large (64-KB each, 4-way) on-chip caches (2-way in Stepping 8 and
higher)
64-KB Level 2 victim cache (16-way)
Two large TLBs (128 entries each, 8-way)
Branch Target Address Cache with 1k entries each identifying 2 branches
Unique and sophisticated branch prediction mechanisms
Bus speeds up to 133 MHz
Extremely low power dissipation
Very small die-52 mm2 in TSMC 0.13μ technology (47 mm2 for Stepping 8
and higher)
2.2 Onboard Chipsets
2.2.1 Northbridge and Southbridge Chipsets
The following chipsets are preinstalled on the board:
Northbridge : Intel® 815E
Southbridge : Intel® ICH2
The following two sections (Section 2.2.2 and Section 2.2.3) list some of the features of
the Intel® 815E and the Intel® ICH2 chipsets. For more information on these two chipsets
please refer to the Intel website.
2.2.2 Intel® 815E Northbridge Chipset
The Intel® 815E northbridge chipset comes with the following features:
Flexible processor support ranging from the Intel Celeron processor - Ultra
Low Power at 300MHz to the Pentium III processor - Low Power at 700 MHz
and the Celeron processor at 566 MHz to the Pentium III processor with 512K
cache at 1.26 GHz and beyond with support for 66, 100, or 133 MHz
Processor Side Bus (PSB) speeds
Increased I/O bus bandwidth through the use of Intel Hub Architecture which