IEI Integration ROCKY-3786 v4.0 - Manual (Page 23)

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ROCKY-3786EV CPU Card
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level one cache
256-KB Integrated Full Speed level two cache allows for low latency on
read/store operations
Double Quad Word Wide (256 bit) cache data bus provides extremely high
throughput on read/store operations.
8-way cache associativity provides improved cache hit rate on reads/store
operations.
Error-correcting code for System Bus data
Enables systems which are scaleable for up to two processors
2.1.2 Celeron®
The Intel® Celeron® CPU comes with the following features:
300, 366, 433, 566, 733, 850 MHz, and 1.2 GHz processor speeds
32K L1 cache (16K code and 16K data)
128K integrated L2 cache; 256K for 1.2 GHz
High performance floating-point unit
Intel® MMX™ technology
66 MHz Processor Side Bus (PSB) for 300 - 733 MHz processor speeds, and
100 MHz PSB for 850 MHz and 1.2 GHz
Compatible with 370 pin Socket specifications
Compatible with Intel® 815, 815E, 810 and Intel® 440BX chipsets (except 1.2
GHz)
1.2 GHz supported by Intel® 815/E, 810E2 chipsets
Flip-Chip Pin Grid Array (FC-PGA2) package (for 1.2 GHz)
Flip-Chip Pin Grid Array (FC-PGA) package (566, 733 and 850 MHz)
Plastic Pin Grid Array (PPGA) package (300, 366, and 433 MHz)
Built-in Self Test (BIST)
2.1.3 VIA® C3
The VIA® C3 CPU comes with the following features:
Padlock Advanced Cryptography Engine (available in Stepping 8 and higher).
Padlock Random Number Generator (available in Stepping 3 and higher).
Plug-compatible with Socket 370 processors in terms of bus protocol,