Teledyne LeCroy Protocol PCI Express Script Automation Test Tool - Manual (Page 51)

Teledyne LeCroy PCI Express Script Automation Test Tool User Manual
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3.2.2.2 Test 1-2. TXN_BFT_CompletionTimeout
ASSERTIONS COVERED: TXN.8.0#1.1, TXN.8.0#2, TXN.8.0#3, TXN.8.0#4, TXN.8.0#5
Verify Basic Completion Timer requirements of a Root Complex device. The Completion Timeout timer must not
expire in less than 50 µs, but it must expire if a Request is not completed in 50 ms.
Trainer Stimulus: trans_1-2_TXN_BFT_CompletionTimeout.peg
Recording Options: link_layer.rec
Verification Scripts: trans_1-2_TXN_BFT_CompletionTimeout.pevs
Test Algorithm:
1. Issue command to the Driver to read and reflect to the link the value of the Uncorrectable Error Severity
register for the Root or Switch port to which the Device Emulator is attached. The Verification script uses
this value to determine how Completion Timeout and Unexpected Completion errors should be reported.
2. Issue command to the Driver to clear all error status bits for the Root or Switch port to which the Device
Emulator is attached.
3. Issue command to the Driver to perform a Tag synchronization sequence (if needed) to ensure the next
transaction is done with an expected Tag value.
4. Issue command to the Driver to perform a Memory Read transaction.
5. Wait for the Memory Read Request, then wait for 49 microseconds and issue Memory Read Completion.
6. Issue command to the Driver to reflect the current values of the Error Reporting Registers for the port to
which the Device Emulator is attached (using Configuration Writes).
7. Issue command to the Driver to perform a Tag synchronization sequence (if needed) to ensure the next
transaction is done with an expected Tag value.
8. Issue command to the Driver to perform a Memory Read transaction.
9. Wait for the Memory Read Request, then wait for 50 milliseconds plus 1 microsecond and issue Memory
Read Completion.
10. Issue command to the Driver to reflect the current values of the Error Reporting Registers for the port to
which the Device Emulator is attached (using Configuration Writes).
Pass/Fail Criteria:
Test should successfully progress though all test stages.
All test stages should be executed without protocol violations.
Verify that:
a) The following error conditions are set by the DUT:
• No errors are set in error registers in step 6.
• The ERR_NONFATAL and/or ERR_FATAL bits are set in the Device Status register in step 10,
depending on the severity of the Completion Timeout and Unexpected Completion errors.
• The Completion Timeout and Unexpected Completion error bits are set in the Advanced Uncorrectable
Error Status register (if implemented) in step 10.
• No errors are set in the Advanced Correctable Error Status register (if implemented) in step 10.
• Error bits are set in the Root Error Status register (if implemented) in step 10, depending on the severity of
the Completion Timeout and Unexpected Completion errors.
If the DUT meets all these criteria, the DUT passes the test.