Teledyne LeCroy PCI Express 3.0 Mid-Bus Probe - Manual (Page 6)

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2
6
2 Probe Components
• Y-Cable to Analyzer
• Gen3 Mid-Bus Probe Pod
• Probe Header Cable Assembly
• Probe Connector (mounted to board)
• Clocking Cable Cable* (not shown)
* The Intel-based mid-bus footprint specification only supplies differential lane signaling and ground
reference. Should a reference clock (RefClk) be required a separate connection must be made. Teledyne
LeCroy PCI Express protocol analyzers can use a reference clock probe in conjunction with the mid-bus
analysis. Each mid-bus probe is equipped with one clock probe. The mid-bus reference clock probe is
designed to facilitate capturing clock signals from the system board in the two configurations
recommended by the Intel guideline, i.e., a tap off of an existing clock or a dedicated clock.