Teledyne LeCroy PCI Express 3.0 Mid-Bus Probe - Manual (Page 12)

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2
12
4 Electrical Design
4.1 Probe Loading Effect
The logical probing of the PCI Express bus is achieved by tapping a small amount of energy from the
probed signals and channeling this energy to the analyzer. To avoid excessive loading conditions, the
Teledyne LeCroy mid-bus probe employs high impedance tip resistors (isolation resistors). The probe
isolation resistance is selected to both satisfy the probe sensitivity and system parasitic load
requirements.
Extensive care has been taken to reduce the parasitic effect of the probed signals during each phase of
the mid-bus probe design. The equivalent load model of the Mid-bus probe is available in HSPICE
parameters. It is an empirical-based model that involves complicated connectivity. It can be requested
from the Teledyne LeCroy Protocol Systems Group support team ([email protected])
With this unique design, the Teledyne LeCroy mid-bus probes can capture bus traffic signals with
amplitudes specified by the PCI Express standard, while introducing only slight loss and jitter on the
channel under test. To determine the exact numbers, customers are encourage to simulate their channel
using Teledyne LeCroy’s model.
4.2 Overview of Probe - Pin Assignments
Cross-references from the PCI Express Mid-Bus Probing Footprint and Pinout (8/05/03) Revision 1.0 are
given in tables listed below.
The Summit T3-16 PCI Express analyzers from Teledyne LeCroy support a lane swizzling feature which
allows pairs of differential pin assignments to be re-wired dynamically to match the configuration under
the probe. This also provides additional versatility in the case where two busses are mapped to the probe
footprint and cannot be uniquely positioned within a quadrant. Lane swizzling allow you to reorder
upstream lanes or recorder downstream lanes regardless of the order of physical connections – however,
you cannot interchange upstream lanes with downstream lanes.
In the pinout tables that follow, the following variations may be applied:
• The designation of upstream and downstream may be reversed as long as it is reversed for every
lane (all upstream connections on the left and all downstream on the right may be swapped)
• Lane ordering may be reversed if done as a whole such that probe lanes 0, 1, 2, 3, 4, 5, 6, 7
connect to physical lanes 7, 6, 5, 4, 3, 2, 1, 0. Note that the Summit T3-16 analyzer provides the
flexibility to reorder lanes regardless of the order in which they are physically connected (lane
swizzling).
• Each differential signal pair may have the D+ and D- assignment reversed.