Teledyne LeCroy PCI Express 3.0 Mid-Bus Probe - Manual (Page 10)

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2
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3.4 Probe Keepout Volume
As with any connection to a PCB, sufficient clearance must be allowed around the point where the probe
will connect. This is defined as the keep-out volume, which must be kept clear of other components
mounted on the PCB.
The probe keepout volumes are shown in the diagrams in Section 3.1
3.5 Reference Clock Probe Attachment
Should SSC clocking be used in the system under test or if the link varies the bit rate by more than 100
MHz ± 300ppm (see Section 4.3.7 of Base Spec 3.0), a reference clock tap may be required. The
connection from the reference clock to the analyzer is a 3-pin header (1 by 3, 0.050” center spacing)
which is placed on the clock signal transmission line of the DUT. The PE014UCA-X Reference Clock
Cable provides a three-pin micro socket that connects from this header to the CLK IN port on the Mid-Bus
Pod.
If the reference clock is sampled by tapping off an existing clock, the header shall be located on the
existing clock transmission line, where a high impedance clock probe from the mid-bus probe is
connected with no significant loading effects. In the case of a dedicated clock, the header shall be
located at the end of a dedicated clock transmission line without termination, where a 50-Ohm cable is
connected and the termination for the clock signal is provided on the mid-bus probe board.
The connectivity of the clock header pins follows the following table:
Signal Pin Number
REFCLKp 1 (or 3)
Unused 2
REFCLKn 3 (or 1)
Note that the analyzer is not sensitive to the polarity of the reference clock. Therefore, the probe can be
plugged onto the pin header in either orientation.
The following 3-pin header can be used for the reference clock:
Samtec Part No: TMS-103 (Vertical Orientation)
The reference clock is captured separately with a dedicated probe cable. Considering the possibility that
one clock may be shared between two physically separated mid-bus probes, each mid-bus probe pod is
equipped with a reference clock output port. The reference clock probe can capture signals from the
target system or receive a duplicated reference clock from another mid-bus probe board.
3.6 Daisy Chain Cable (for x16 applications)
A single mid-bus probe pod can capture traffic on bus widths up to x8. If x16 lane widths are required
(e.g., when using a Summit T3-16 Analyzer with a x16 device), two Mid-Bus Probe Pods are required.
In this configuration, one of the pods is connected to the DUT to tap the Reference Clock signal, and the
second pod is “daisy-chained” to the first pod using the PE009UCA-X Daisy Chain Cable. Connect the
Ref Clock cable to the CLK IN port of the first pod, and connect the Daisy Chain Cable between the CLK
OUT port of the first pod and the CLK IN port of the second pod.