AMD Am79C930 - Manual (Page 125)

P R E L I M I N A R Y AMD
125 Am79C930
When written with a 1, the PWRDWN bit generates an interrupt to
the 80188, requesting that the 80188 core place the Am79C930 de-
vice into the power down state. The interrupt is signaled in MIR0, bit
5. If written with a 0 while in power down mode, power down mode is
exited. When written with a 1, value read will remain 0 until the de-
vice actually enters the power down mode.
1 Interrupt – Represents the internal interrupt level. This signal remains true un-
til the interrupt has been serviced (not pulse generated).
0 Reserved – Read only as a 0.
PCMCIA Card Information Structure (CIS)
The PCMCIA CIS space has been allocated to reside in
the flash memory space of a design based on the
Am79C930 device. This space corresponds to 1K–16
bytes of the uppermost 1K of flash memory. Since only
even addressed bytes of attribute memory space are
defined to exist in the PCMCIA specification, only even
addresses of the 2K–32 CIS range will map into the flash
memory, and hence, the 2K–32 address range for the
Am79C930 CIS space is mapped to only 1K–16 bytes of
flash space. Note that the address range is limited to 2K–32 rather
than a complete 2K of space. This is because the upper-
most 16 bytes of the flash memory must be reserved for
the initial instructions for the 80188 core, since the
80188 core will automatically access these locations for
its initial instruction fetch following a Am79C930 device
reset operation.