Atec Tektronix-TLA700 Series - Manual (Page 3)

L O G I C A N A L Y Z E R S • T L A 7 0 0 S E R I E S 3
External Clock Input –
Polarity: positive or negative.
Threshold: –2.56 V to +2.54 V, nominal; program-
mable in 20 mV increments.
Sensitivity:
≤ 500 mV
p-p
.
Impedance: 1 k
Ω
terminated to ground.
Data Depth –
256 K full channel/512 K half channel.
1 M full channel/2 M half channel (optional).
PATTERN SEQUENCING CHARACTERISTICS
Blocks – Separate sections of pattern program
that are output in a user definable order by the
Sequencer. Block pattern depth can be from 40
sequences (full channel mode) or 80 sequences
(half channel mode) up to the entire depth of the
TLA 7PG2. A maximum of 4,000 Blocks may be
defined.
Sequencer – A 4000 line memory that allows
the user to pick the output order of individual
Blocks. Each line in the sequencer allows the defi-
nition of a Block to be output, a Repeat Count for
that Block, A Wait For event condition for the
Block, the Signal state for that Block (asserted or
unasserted), and a Jump If event condition, with
a sequence line to jump to if the condition is
satisfied.
Sub-Sequences – Up to 50 contiguous lines of
the Sequencer memory may be defined as a Sub-
Sequence. A Sub-Sequence can then be treated
like a block. (Example: 15 Sequences of Blocks
are defined as Sub-Sequence A1. Now any line in
the Sequencer can output A1. Five calls to Sub-
Sequence A1 will be flattened out to 75
sequences at run time.)
Jump If – Jumps to the specified sequence if a
user defined event is true. The user defined event
is a boolean combination of the eight external
event input lines and the one-of-four intermodule
signals. The user defined Event is selectable
between level and edge (event going from false
to true). One Jump If may be defined for every
Block. The Jump If command works at all clock
rates, including the maximum half channel mode
rate of 268 MHz.
Wait For – Pattern output is paused until the
user defined Event is true. One Wait For may be
defined for every Block.
Assert Signal – One of the four inter-module
signals is selected to be controlled from the pat-
tern generator program. Signals may be asserted
and unasserted allowing true interaction with the
logic analyzer modules and with other pattern
generator modules. Signal action (assert or
unassert) may be defined for every Block.
Repeat Count – The sequence is repeated from
1 to 65,536 times. Infinite may also be selected.
One Repeat Count may be defined for every
Block. Note that a Repeat value of 10,000 takes
one sequence line in memory, not 10,000.
Step – While in Step mode, the TLA 7PG2, the
user can manually satisfy (i.e., click an icon) Wait
For and Jump conditional events. This allows the
user to debug the logic flow of the program’s
sequencing.
Initialization Block – The unconditional Jump
command allows the user to implement an equiv-
alent function.
COMMON TO P6470 TTL/CMOS & P6471
ECL PROBES
Number of Data Outputs –
16 in Full Channel Mode.
8 in Half Channel Mode.
Number of Clock Outputs – 1.
(Only one of Clock Output and Strobe Output can
be enabled.)
Number of Strobe Outputs – 1.
(Only one of Clock Output and Strobe Output can
be enabled.)
Number of External Event Input – 2.
Clock Output Polarity – Positive.
Strobe Type – RZ only.
Strobe Delay – Zero or Trailing Edge.
P6470 TTL/CMOS PROBE
Output Type –
HD74LVC541A for Data Output.
HD74LVC244A for Clock/Strobe Output.
Rise/Fall Time (20% to 80%) –
Timing values Timing values
measured using measured using
75 Ω termination 75 Ω termination
(internal to probe), (internal to probe),
1 M Ω + <1 pF 510 Ω + 51 pF
load and V
OH
load and V
OH
set to 5.0 V set to 5.0 V
Clock/Strobe Output:
Rise: 640 ps typical 6.5 ns typical
Fall: 1.1 ns typical 6.3 ns typical
Data Output:
Rise: 680 ps typical 5.2 ns typical
Fall: 2.9 ns typical 4.5 ns typical
Output Voltage (nominal, load: 1 M
Ω
) –
V
OH
: 2.0 V to 5.5 V, tri-stateable, programmable in
25 mV increments.
V
OL
: 0 V.
Data Output Skew –
< 510 ps typical between all data output pins of
all modules in the mainframe after inter-module
skew is adjusted manually.
< 480 ps typical between all data output pins of
single probe.
Data Output to Strobe Output Delay –
1.7 ns typical when strobe delay set to zero.
Data Output to Clock Output Delay –
2.4 ns typical.
External Clock Input to Clock Output
Delay –
Full Channel mode: 61.5 ns typical.
Half Channel mode: 61.5 ns typical.
Number of External Inhibit Input – 1.
External Inhibit Input to Output Enable
Delay – 34 ns typical for Data Output.
External Inhibit Input to Output Disable
Delay – 86 ns typical for Data Output.
Probe D Data Output to Output Enable
Delay – (for Internal Inhibit) 7 ns typical for Data
Output.
Probe D Data Output to Output Disable
Delay – (for Internal Inhibit) 8 ns typical for Data
Output.
External Event Input to Clock Output Setup
(for inhibit) (event-filter: off) –
Full Channel mode: 1.5 clocks + 150 ns typical.
Half Channel mode: 2 clocks + 150 ns typical.
External Event Input and Inhibit Input –
Input Type: 74LVC14A.
Minimum Pulse Width: 100 ns.
P6471 ECL PROBE
Output Type –
100E151 for data output.
100EL16 for strobe output.
100EL04 for clock output.
All outputs are unterminated.
Rise/Fall Time (20% to 80%) –
Timing values measured
using 51 Ω s to –2.0 V
Clock Output:
Rise: 320 ps typical
Fall: 330 ps typical
Data Output:
Rise: 1200 ps typical
Fall: 710 ps typical
Strobe Output:
Rise: 290 ps typical
Fall: 270 ps typical
Data Output Skew –
<170 ps typical between all data output pins of all
modules in the mainframe after inter-module
skew is adjusted manually.
<140 ps typical between all data output pins of
single probe.
Data Output to Strobe Output Delay –
2.94 ns typical when strobe delay set to zero.
Data Output to Clock Output Delay –
780 ps typical.
External Clock Input to Clock Output
Delay – 51 ns typical.
External Event Input –
Input Level: ECL.
Input Type: 10H116.
Minimum Pulse Width: 50 ns.
Pat t e r n G e n e r at o r M o d u l e
P h y s i c a l C h a r a c t e r i s t i c s
Dimensions mm in.
Height 262 10.3
Width 61 2.4
Depth 381 15
Weight kg lb.
Net 3.0 6.5
Shipping 6.2 13.5
P6470 Probe Cable Length – 1.6 m (5 ft.)
P6471 Probe Cable Length – 1.6 m (5 ft.)
Characteristics