Atec Tektronix-TLA700 Series - Manual (Page 2)

L O G I C A N A L Y Z E R S • T L A 7 0 0 S E R I E S 2
Logic Analyzer Modules
GENERAL
Number of Channels per Module (all chan-
nels are acquired including clocks) –
TLA 7N1: 34 channels (2 are clock/qualifier
channels).
TLA 7N2, TLA 7P2: 68 channels (4 are clock/
qualifier channels).
TLA 7N3: 102 channels (4 are clock/qualifier and
2 are qualifier channels).
TLA 7N4, TLA 7P4: 136 channels (4 are
clock/qualifier and 4 are qualifier channels).
Channel Grouping – No limit to number of
groups or number of channels per group (all
channels can be reused in multiple groups).
Module “Merging” – Three 102 channel or 136
channel modules can be “merged” to make up to
a 408 channel module. Merged modules exhibit
the same depth as the lesser of the three individ-
ual modules. Word/range/setup-and-
hold/glitch/transition recognizers span all three
modules. Only one set of clock connections is
required.
Time Stamp – 50 Bits at 500 ps resolution (6.5
day range).
Clocking/Acquisition Modes- State, timing,
simultaneous.
Number of Mainframe Slots Required – 2.
INPUT CHARACTERISTICS (WITH P6417,
P6418 OR P6434 PROBES)
Capacitive Loading –
1.4 pF typical data; 2 pF typical clock (P6418).
2 pF typical (P6417 & P6434).
Threshold Selection Range – From +5.0 V
to –2.0 V in 50 mV increments.
Threshold Selection Channel Granularity –
Separate selection for clock (1) and data (16) for
each 17 channel probe connector.
Threshold Accuracy (including probe) –
±100 mV.
Input Voltage Range –
Operating: 6.5 V
P-P
centered around the pro-
grammed threshold.
Non-destructive: ±15 V.
Input Signal Swing (probe overdrive) –
±250 mV or ±25% of signal swing, whichever is
greater (P6417 & P6418).
±300 mV or ± 25% of signal swing (P6434).
Input Signal Minimum Slew Rate –
200 mV/ns typical.
STATE ACQUISITION CHARACTERISTICS
(WITH P6417, P6418 OR P6434 PROBES)
Maximum Synchronous Clock Rate –
100 MHz standard, 200 MHz optional.
Maximum Data Rate (Half Channels) –
400 MHz, typical. Requires 200 MHz state option.
State Memory Depth – 64 K, 256 K, 1 M, 4 M
or 16 M bits per channel.
Setup Time Selection Range – From 8.5 ns
before, to 7.0 ns after clock edge.
Setup-and-hold Window – 2.0 ns typical.
Minimum Clock Pulse Width – 2 ns.
Active Clock Edge Separation – 5 ns.
Demux Channel Selection – 32 channels can
be demultiplexed to other channels through user
interface; for all channels contact local Tektronix
account manager.
TIMING ACQUISITION CHARACTERISTICS
(WITH P6417, P6418 OR P6434 PROBES)
Main Timing Resolution – 4 ns to 50 ms.
Main Timing Resolution with Glitch Storage
Enabled – 10 ns to 50 ms.
Main Timing Memory Depth (with or with-
out transitional storage enabled) – 64 K,
256 K, 1 M, 4 M or 16 M bits per channel.
Main Timing Memory Depth with Glitch
Storage Enabled – Half of default main
memory depth.
MagniVu – 500 ps.
MagniVu Timing Memory Depth – 2 Kbits
(2048) per channel.
Channel-to-channel Skew –
≤ 1 ns typical.
Minimum Recognizable Pulse Width (single
channel) – 2 ns.
Minimum Recognizable Glitch Width (single
channel) – 2 ns.
Minimum Recognizable Multi-channel
Trigger Event – Sample period + 2 ns.
TRIGGER CHARACTERISTICS
Independent Trigger States – 16.
Maximum Independent If/then Clauses per
State – 16.
Maximum Number of Events per If/then
Clause – 8.
Maximum Number of Actions per If/then
Clause – 8.
Maximum Number of Trigger Events – 18
(2 counter/timers plus any 16 other resources).
Number of Word Recognizers – 16.
Number of Range Recognizers – 4.
Number of Counter/Timers – 2.
Trigger Event Types – Word, group, channel,
transition, range, anything, counter value, timer
value, signal, glitch, setup-and-hold violation.
Trigger Action Types – Trigger module, trigger
all, store, don’t store, start store, stop store, incre-
ment counter, reset counter, start timer, stop
timer, reset timer, goto state, set/clear signal, do
nothing.
Trigger Sequence Rate – DC to 250 MHz
(4 ns).
Counter/Timer Range – 51 bits each (>100
days @ 4 ns).
Counter Rate – DC to 250 MHz (4 ns).
Timer Clock Rate – 250 MHz (4 ns).
Counter/Timer Latency – None (can be tested
or reset immediately after starting).
Range Recognizers – Double bounded (can be
as wide as any group, must be grouped accord-
ing to specified order of significance).
Setup-and-hold Violation Recognizer Setup
Time Range – From 8 ns before to 7 ns after
clock edge in 0.5 ns increments.
Setup-and-hold Violation Recognizer Hold
Time Range – From 7 ns before to 8 ns after
clock edge in 0.5 ns increments.
Trigger Position – Any data sample.
MagniVu Trigger Position – MagniVu data is
centered around the module trigger.
Storage Control (data qualification) – Global
(conditional), by state (start/stop), by trigger
action, or transitional.
Storage Window Granularity – Single sample
or block-of-31 samples before and after.
Lo g i c A n a ly z e r M o d u l e
P h y s i c a l C h a r a c t e r i s t i c s
Dimensions mm in.
Height 262 10.3
Width 61 2.4
Depth 381 15
Weight kg lb.
Net 3.1 6.7
Shipping 6.3 13.7
P6417 Probe Cable Length – 1.8 m (6 ft.).
P6418 Probe Cable Length – 1.9 m (6.25 ft.).
P6434 Probe Cable Length – 1.5 m (5 ft.).
All three probes have the same electrical length.
Pattern Generator Module
GENERAL
Data Width –
64 Channel full channel mode.
32 Channel half channel mode.
Module “Merging” – Five modules can be
“merged” to make up to a 320 channel module.
Merged modules exhibit the same depth as the
lesser of the 5 individual modules.
Number of Mainframe Slots Required – 2.
Data Rate –
Internal Clock:
0.5 Hz to 134 MHz full channel mode.
1.0 Hz to 268 MHz half channel mode.
External Clock:
DC to 134 MHz full channel mode.
DC to 268 MHz half channel mode.
Characteristics