Atec Agilent-N6030A - Manual (Page 9)

9
External triggers
Number of inputs
8 each (4 SMB female front-panel
connectors plus four software triggers
over the PCI backplane from host
processor)
Trigger polarity
Negative/positive
Trigger impedance
2 k Ω
Maximum input level
±4.5 volts
Input sensitivity
250 mV
Trigger threshold
-4.3 volts to +4.3 volts
Trigger timing resolution
Clock/8 (6.4 ns at full rate)
Trigger latency
34 * Clk/8 (217.6 ns at full rate)
Trigger uncertainty
< 50 ps
Minimum trigger width
12.8 ns at full clock rate
Trigger delay
Programmable from 1 to 256 sync
clock cycles with 1 sync clock cycle
resolution 1
External markers
Markers can be defined for each
waveform segment.
Number of outputs
4 each SMB female
Marker polarity
Negative, positive
Output impedance
50 Ω
Marker low level
100 mV nominal into high impedance
load
Marker high level
3.2 Volts nominal into high impedance
load
Marker timing resolution
Clock/8 (6.4 ns at full rate)
Marker latency
Marker precedes analog output and
is adjustable in 2 sample clock period
steps.
Marker latency repeatability
< 100 ps
Marker width
Programmable from 1 to 256 sync
clock cycles
Marker delay
Programmable from -8 to 502 sample
clock cycles, with 2 sample clock
cycle resolution
Module synchronization
Supports system scaling for any
number of N6030A modules. A
single module can support fan-out
of 8 N6030A modules for precise
triggering and repeatability. Driver
boards may be used to scale any
number of modules.
Sync clock output level
800 mV p-p (50 Ω, AC coupled)
Sync clock input sensitivity
100 mV p-p minimum into 50 Ω AC
coupled
Analog output
Output connector
SMA female
Output impedance
50 Ω
Analog output levels
The following output levels are
specified into 50 Ω
Single-ended Differential
Passive mode 0.5 Vp-p N/A
Active mode 1 Vp-p with
±0.2 V offset N/A
Direct DAC
mode
N/A 1 Vp-p
(0 volt offset)
Uncorrected passband flatness
±1 dB DC - 200 MHz;
±2.5 dB DC - 500 MHz
(with 1.25 GHz clock)
Uncorrected passband group delay
±500 ps DC - 200 MHz;
±1 ns DC - 500 MHz
(with 1.25 GHz clock)
Reconstruction filters
500 MHz and 250 MHz realized as
7-pole Cauer Chebychev filters plus
thru-line output
Pulse response
Rise time (10 to 90%): < 1 ns
Fall time (10 to 90%): < 1 ns
Amplitude: 0.5 Vp-p
Key characteristics
(continued)
1. A sync clock cycle is clock/8.