Atec Anritsu-MP1763C-64C-64D - Manual (Page 3)

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Error Detector Application Software
High Input Sensitivity And Wide Phase Margin
• Input sensitivity: 50 mVp-p
(typical value at 10 Gbit/s, PRBS 2
23 – 1)
• Phase margin: 70 ps or more
(typical value at 10 Gbit/s, PRBS 2
23 – 1)
Eye Margin Measurement
The phase margin and threshold margin can be measured and dis-
played for any error rate.
Burst Measurement
• The burst data can be measured even for the PRBS and pro-
grammable patterns.
• High-speed synchronization gain is achieved by a quick synchro-
nous method (typical sync. gain time at 10 Gbit/s, programmable
pattern length of 2048 bits, sync. threshold at 10
–2 : 850 ns).
Selectivity BER Measurement In Bit Units
The bit errors can be measured for any block of 32-bit segments or
any bit.
Error Analysis Function (Option)
The pattern (256 bits in total) before and after a bit in which an
error occurred can be displayed. Also, insertion and omission
errors are displayed using different LED colors.
Differential Input Support (Option)
• This supports direct input of high-speed differential signals used
by high-speed devices, buses and backplanes, such as XAUI,
SFI-4 P2 4 Lane and PCI Express.
• Detailed evaluation is possible because independent thresholds
can be set for inverted and non-inverted data
Clock Recovery Function (Option)
• The clock is recovered from the input data for use as a trigger
signal at error rate detection and waveform monitoring.
Evaluation does not require an external clock and the recovered
clock can also be used as an external clock, depending on the
setting.
• A wide range of bit rates from 62.5 Mbit/s to 11.1 Gbit/s is sup-
ported, along with the 4.25 Gbit/s rate used by Fibre Channel.
• When used in conjunction with differential input, it is also possible
to evaluate the latest high-speed differential devices that do not
use a clock without the need for an external jig.
MX176400A Q/Eye Analysis Software
• Eye diagram and eye margin automatic measurement
• Displays a mask figure for the evaluation on the screen
• Q-factor (ITU-T G.976) automatic measurement
∗
Single input unsupported; use at differential signal input is not supported.
MX176401A SDH/SONET Pattern Editor
• Support OC-1 (STM-0) to OC-192c (STM-64c) mapping
• Alarm addition (OOF, LOF, MS-AIS, REI, RDI)
• BIP error addition (B1, B2, B3)
• Support “No frame” pattern
MX176403A GbE/10GbE Pattern Editing Software
(At Order Acceptance)
• Supports Gbit Ethernet, 10 Gbit Ethernet (10GBASE-R, XAUI)
frames
• 8B/10B, 64B/66B ON/OFF
• Header, Payload editing function
• CRC Auto-calculation
• Bit Error, FCS Error insertion function
MP1763C/1764C_E 04.6.24 3:02 PM Page 3