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2 chipset, Chipset -18, Chapter 3 – Asus M4N98TD EVO User Manual

Page 74: Northbridge chipset configuration, Dram controller configuration, Channel interleaving [xor of address bit, Memclk tristate c3/atlvid [disabled, Dct unganged mode [always, Power down enable [disabled

2 chipset, Chipset -18, Chapter 3 | Northbridge chipset configuration, Dram controller configuration, Channel interleaving [xor of address bit, Memclk tristate c3/atlvid [disabled, Dct unganged mode [always, Power down enable [disabled | Asus M4N98TD EVO User Manual | Page 74 / 118 2 chipset, Chipset -18, Chapter 3 | Northbridge chipset configuration, Dram controller configuration, Channel interleaving [xor of address bit, Memclk tristate c3/atlvid [disabled, Dct unganged mode [always, Power down enable [disabled | Asus M4N98TD EVO User Manual | Page 74 / 118