Rainbow Electronics MAX1637 - Manual (Page 18)

MAX1637
P(gate) = Q g x
ƒ
x V GG
where Q g is the sum of the gate-charge values for low-
side and high-side switches. For matched MOSFETs,
Q
g is twice the data-sheet value of an individual
MOSFET. Efficiency can usually be optimized by con-
necting V
GG to the most efficient 5V source, such as
the system +5V supply.
P(diode) = diode conduction losses = I LOAD x V FWD
x t D x
ƒ
where t D is the diode conduction time (120ns typ), and
V FWD is the diode forward voltage. This power is dissi-
pated in the MOSFET body diode if no external
Schottky diode is used.
P(cap) = input capacitor ESR loss = I RMS
2 x R ESR
where I RMS is the input ripple current as calculated in
the Input Capacitor Value section.
Light-Load Efficiency Considerations
Under light loads, the PWM operates in discontinuous
mode. The inductor current discharges to zero at some
point during the charging cycle. This makes the induc-
tor current’s AC component high compared to the load
current, which increases core losses and I
2 R losses in
the input-output filter capacitors. For best light-load effi-
ciency, use MOSFETs with moderate gate-charge lev-
els and use ferrite MPP or other low-loss core material.
Avoid powdered-iron cores; even Kool-Mu (aluminum
alloy) is not as desirable as ferrite.
Low-Noise Operation
Noise-sensitive applications such as hi-fidelity multi-
media-equipped systems, cellular phones, RF commu-
nicating computers, and electromagnetic pen-entry
systems should operate the controller in PWM mode
(SKIP = high). This mode forces a constant switching
frequency, reducing interference due to switching
noise by concentrating the radiated EM fields at a
known frequency outside the system audio or IF bands.
Choose an oscillator frequency for which switching-
frequency harmonics do not overlap a sensitive fre-
quency band. If necessary, synchronize the oscillator
to a tight-tolerance external clock generator.
Powering From a Single
Low-Voltage Supply
The circuit of Figure 7 is powered from a single 3.3V to
5.5V source and delivers 4A at 2.5V. At input voltages
of 3.15V, this circuit typically achieves efficiencies of
90% at 3.5A load currents. When using a single supply
to power both V
BATT and V BIAS , be sure that it does not
exceed the 5.5V rating (6V absolute maximum) for V GG
and V CC . Also, heavy current surges from the input
may cause transient dips on V CC . To prevent this, the
decoupling capacitor on V CC may need to be
increased to 2µF or greater. This circuit uses low-
threshold (specified at V
GS = 2.7V) IRF7401 MOSFETs
which allow a typical startup of 3.15V at above 4A. Low
input voltages demand the use of larger input capaci-
tors. Sanyo OS-CONs are recommended for their high
capacity and low ESR.
PC Board Layout Considerations
Good PC board layout is required to achieve specified
noise, efficiency, and stable performance. The PC
board layout artist must be given explicit instructions,
preferably a pencil sketch showing the placement of
power-switching components and high-current routing.
See the PC board layout in the MAX1637 evaluation kit
manual for examples. A ground plane is essential for
optimum performance. In most applications, the circuit
will be located on a multi-layer board, and full use of
the four or more copper layers is recommended. Use
the top layer for high-current connections, the bottom
layer for quiet connections (REF, CC, GND), and the
inner layers for an uninterrupted ground plane. Use the
following step-by-step guide:
1) Place the high-power components (C1, C2, Q1, Q2,
D1, L1, and R1) first, with their grounds adjacent.
• Minimize current-sense resistor trace lengths and
ensure accurate current sensing with Kelvin con-
nections (Figure 8).
• Minimize ground trace lengths in the high-current
paths.
• Minimize other trace lengths in the high-current
paths.
— Use >5mm-wide traces.
— CIN to high-side MOSFET drain: 10mm
max length
— Rectifier diode cathode to low side
— MOSFET: 5mm max length
— LX node (MOSFETs, rectifier cathode, induc-
tor): 15mm max length
Ideally, surface-mount power components are butted
up to one another with their ground terminals almost
touching. These high-current grounds are then con-
nected to each other with a wide, filled zone of
top-layer copper so they do not go through vias. The
resulting top-layer subground plane is connected to the
normal inner-layer ground plane at the output ground
terminals, which ensures that the IC’s analog ground is
Miniature, Low-Voltage,
Precision Step-Down Controller
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