Rainbow Electronics MAX1083 - Manual (Page 11)

Detailed Description
The MAX1082/MAX1083 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 10-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1082/MAX1083.
Pseudo-Differential Input
The equivalent circuit of Figure 4 shows the MAX1082/
MAX1083’s input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1 and
CH2/CH3. Configure the channels according to Tables
1 and 2.
The MAX1082/MAX1083 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
sinusoidal signal at IN-, the input voltage is determined
by:
The maximum voltage variation is determined by:
A 2.6Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / f
SCLK ). When a DC refer-
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD . The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
C
HOLD
as a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
C
HOLD from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to V
DD1 /2 within the limits of 10-bit resolu-
tion. This action is equivalent to transferring a
12pF x (V
IN + - V IN -) charge from C HOLD to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
max
( )
d
dt
V f
LSB
t
V
t
V
IN
CONV
REF
CONV
IN
−
= − ≤ = 2
1
2
10
π
V V ft
IN IN
− = − ( )sin( ) 2 π
MAX1082/MAX1083
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 10-Bit ADCs with Internal Reference
______________________________________________________________________________________ 11
INPUT
SHIFT
REGISTER CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+1.22V
REFERENCE
T/H
ANALOG
INPUT
MUX
10 + 2-BIT
SAR ADC
IN
DOUT
SSTRB
V DD1
V DD2
GND
SCLK
DIN
COM
REFADJ
REF
OUT
REF
CLOCK
+2.500V
17k
7
8
9
6
11
12
13
14
15
CH1
3
CH2
4
CH3
5
CH0
2
MAX1282
MAX1283
CS
SHDN
1
16
10
2.05 A ≈
Figure 3. Functional Diagram
C HOLD
12pF
R IN
800 Ω
HOLD
INPUT
MUX
C SWITCH *
*INCLUDES ALL INPUT PARASITICS
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1 AND CH2/CH3.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
CH0
REF
GND
CH1
CH2
CH3
COM
ZERO
V DD1 /2
COMPARATOR
CAPACITIVE
DAC
6pF
TRACK
Figure 4. Equivalent Input Circuit