Timing characteristics – Rainbow Electronics MAX1204 User Manual
Page 6

C
LOAD
= 100pF
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
6
_______________________________________________________________________________________
External clock mode only, C
LOAD
= 100pF
ns
240
C
LOAD
= 100pF
ns
ns
20
240
t
DO
SCLK Fall to Output Data Valid
CONDITIONS
240
t
DV
CS Fall to Output Enable
C
LOAD
= 100pF
ns
240
t
TR
CS Rise to Output Disable
t
SDV
CS Fall to SSTRB Output Enable
(Note 6)
External clock mode only, C
LOAD
= 100pF
ns
240
t
STR
CS Rise to SSTRB Output
Disable (Note 6)
Internal clock mode only
ns
0
t
SCK
SSTRB Rise to SCLK Rise
(Note 6)
ns
0
t
DH
DIN to SCLK Hold
µs
1.5
t
ACQ
Acquisition Time
ns
100
t
DS
DIN to SCLK Setup
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
TIMING CHARACTERISTICS
(V
DD
= +5V ±5%, VL = 2.7V to 3.6V, V
SS
= 0V or -5V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
ns
100
t
CSS
CS to SCLK Rise Setup
ns
0
t
CSH
CS to SCLK Rise Hold
ns
200
t
CH
SCLK Pulse Width High
ns
200
t
CL
SCLK Pulse Width Low
C
LOAD
= 100pF
ns
240
t
SSTRB
SCLK Fall to SSTRB
C
LOAD
= 100pF
Note 1:
Tested at V
DD
= 5.0V; V
SS
= 0V; unipolar input mode.
Note 2:
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
calibrated.
Note 3:
Internal reference, offset nulled.
Note 4:
On-channel grounded; sine-wave applied to all off-channels.
Note 5:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
Common-mode range for analog inputs is from V
SS
to V
DD
.
Note 8:
External load should not change during the conversion for specified accuracy.
Note 9:
Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c);
REFADJ = GND.
Note 10:
Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (
CS high). When the outputs are
active (
CS low), the logic supply current depends on f
SCLK
, and on the static and capacitive load at DOUT and SSTRB.
Note 11:
Measured at V
SUPPLY
+5% and V
SUPPLY
-5% only.
Note 12:
Measured at VL = 2.7V and VL = 3.6V.