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Electrical characteristics (continued), Timing characteristics – Rainbow Electronics MAX188 User Manual

Page 5

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Note 1:

Tested at V

DD

= 5.0V; V

SS

= 0V; unipolar input mode.

Note 2:

Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3:

MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.

Note 4:

Ground on-channel; sine wave applied to all off channels.

Note 5:

Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.

Note 6:

Guaranteed by design. Not subject to production testing.

Note 7:

External load should not change during conversion for specified accuracy.

Note 8:

Measured at V

SUPPLY

+5% and V

SUPPLY

-5% only.

Note 9:

The common-mode range for the analog inputs is from V

SS

to V

DD

.

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________

5

PARAMETER

SYMBOL

CONDITIONS

UNITS

Positive Supply Rejection
(Note 8)

PSR

±0.06

±0.5

mV

Negative Supply Rejection
(Note 8)

PSR

V

SS

= -5V ±5%; external reference, 4.096V;

full-scale input

±0.01

±0.5

mV

ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= 5V ±5%; V

SS

= 0V or -5V; f

CLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T

A

= T

MIN

to T

MAX

, unless otherwise

noted.)

TIMING CHARACTERISTICS

(V

DD

= 5V ±5%; V

SS

=0V or -5V, T

A

= T

MIN

to T

MAX

, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

UNITS

SCLK Pulse Width Low

t

CL

200

ns

SCLK Fall to SSTRB

t

SSTRB

C

LOAD

= 100pF

200

ns

t

SDV

External clock mode only, C

LOAD

= 100pF

200

ns

t

STR

External clock mode only, C

LOAD

= 100pF

200

ns

t

SCK

Internal clock mode only

0

ns

Acquisition Time

t

AZ

1.5

µs

DIN to SCLK Setup

t

DS

100

ns

DIN to SCLK Hold

t

DH

0

ns

C

LOAD

= 100pF

20

150

ns

SCLK Fall to Output Data Valid

t

DO

20

200

ns

CS Fall to Output Enable

t

DV

C

LOAD

= 100pF

100

ns

CS Rise to Output Disable

t

TR

C

LOAD

= 100pF

100

ns

CS to SCLK Rise Setup

t

CSS

100

ns

CS to SCLK Rise Hold

t

CSH

0

ns

SCLK Pulse Width High

t

CH

200

ns

MAX18_ _C/E

MAX18_ _M

SSTRB Rise to SCLK Rise
(Note 6)

CS Fall to SSTRB Output Enable
(Note 6)

V

DD

= 5V ±5%; external reference, 4.096V;

full-scale input

MIN

TYP

MAX

MIN

TYP

MAX

CS Rise to SSTRB Output Disable
(Note 6)