Rainbow Electronics MAX1143 - Manual (Page 16)

MAX1142/MAX1143
14-Bit ADC, 200ksps, +5V Single-Supply
with Reference
16 ______________________________________________________________________________________
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX1142/
MAX1143’s calibration scheme. The magnitude of the
offset produced by a synchronous signal depends on
the signal’s shape. Recalibration may be appropriate if
the shape or relative timing of the clock or other digital
signals change, as might occur if more than one clock
signal or frequency is used.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX1142/
MAX1143’s THD (-88dB) at frequencies of interest. If
the chosen amplifier has insufficient common-mode
rejection, which results in degraded THD performance,
use the inverting configuration to eliminate errors from
common-mode voltage. Low temperature-coefficient
resistors reduce linearity errors caused by resistance
changes due to self-heating. To reduce linearity errors
due to finite amplifier gain, use an amplifier circuit with
sufficient loop gain at the frequencies of interest.
DC Accuracy
If DC accuracy is important, choose a buffer with an
offset much less than the MAX1142/MAX1143’s maxi-
mum offset (±6mV), or whose offset can be trimmed
while maintaining good stability over the required tem-
perature range.
Operating Modes and Serial Interfaces
The MAX1142/MAX1143 are fully compatible with
MICROWIRE and SPI/QSPI devices. MICROWIRE and
SPI/QSPI both transmit a byte and receive a byte at the
same time. The simple software interface requires only
three 8-bit transfers to perform a conversion, one 8-bit
transfer to configure the ADC, and two more 8-bit trans-
fers to clock out the 14-bit conversion result.
Mode 1 Short Acquisition Mode (24 SCLK)
Configure short acquisition by setting M1 = 0 and M0 =
0. In short acquisition mode, the acquisition time is 5.5
clock cycles. The total period is 24-clock cycles per
conversion.
Mode 2 Long Acquisition Mode (32 SCLK)
Configure long acquisition by setting M1 = 1 and M0 =
1. In long acquisition mode, the acquisition time is 13.5
clock cycles. The total period is 32 clock cycles per
conversion.
Calibration Mode
A calibration is initiated through the serial interface by
setting M1 = 0, M0 = 1. Calibration can be done in
either internal or external clock mode, though it is desir-
able that the part be calibrated in the same mode in
which it will be used to do conversions. The part will
remain in calibration mode for approximately 80,000
clock cycles, unless the calibration is aborted.
Calibration is halted if
RST or SHDN goes low, or if a
valid start condition occurs.
Software Shut-Down
A software power-down is initiated by setting M1 = 1,
M0 = 0. After the conversion completes, the part shuts
down. It reawakens upon receiving a new start bit.
Conversions initiated with M1 = 1 and M0 = 0 (shut-
down) use the acquisition mode selected for the previ-
ous conversion.
Shutdown Mode
The MAX1142/MAX1143 may be shut down by pulling
SHDN low or by asserting software shutdown. In addi-
tion to lowering power dissipation to 13µW, consider-
able power can be saved by shutting down the
converter for short periods between conversions.
Duration will be affected by REF startup time with inter-
nal reference. There is no need to perform a calibration
after the converter has been shut down, unless the time
in shutdown is long enough that the supply voltage or
ambient temperature may have changed.
Supplies, Layout, Grounding
and Bypassing
For best system performance, use separate analog and
digital ground planes. The two ground planes should
be tied together at the MAX1142/MAX1143. Use pins 3
and 14 as the primary AGND and DGND, respectively.
If the analog and digital supplies come from the same
source, isolate the digital supply from the analog with a
low value resistor (10
Ω
).
The MAX1142/MAX1143 are not sensitive to the order
of AV
DD and DV DD sequencing. Either supply can be
present in the absence of the other. Do not apply an
external reference voltage until after both AV
DD
and
DV DD are present.
Be sure that digital return currents do not pass through
the analog ground. All return current paths must be
low-impedance. A 5mA current flowing through a PC
board ground trace impedance of only 0.05
Ω
, creates
an error voltage of about 250µV, or about 2LSBs error
with a ±4V full-scale system. The board layout should
ensure that the digital and analog signal lines are kept
separate. Do not run analog and digital lines parallel to
one another. If you must cross one with the other, do so
at right angles.
The ADC is sensitive to high-frequency noise on the
AV
DD power supply. Bypass this supply to the analog
ground plane with 0.1µF. If the main supply is not ade-