Rainbow Electronics ISD5100 - Manual (Page 73)

ISD5100 – SERIES
Publication Release Date: October, 2003
- 73 - Revision 0.2
Master Reads from Slave immediately after first byte (Read Mode)
R/W
From
Master
Start Bit
From
Master
Stop Bit
From
Master
acknowledgement
from slave
acknowledgement
from Master
not-acknowledged
from Master
acknowledgement
from Master
From Master
From Slave From Slave From Slave
S R A A A N P Low ADDR BYTE SLAVE ADDRESS STATUS W ORD High ADDR. BYTE
Another common operation in the ISD5100 Series is the reading of digital data from the chip’s memory
array at a specific address. This requires the I
2 C interface Master to first send an address to the
ISD5100 Series Slave device, and then receive data from the Slave in a single I 2 C operation. To
accomplish this, the data direction R/W bit must be changed in the middle of the command. The
following example shows the Master sending the Slave address, then sending a Command Byte and 2
bytes of address data to the ISD5100-Series, and then immediately changing the data direction and
reading some number of bytes from the chip’s digital array. An unlimited number of bytes can be read
in this operation. The “N” not-acknowledge cycle from the Master forces the end of the data transfer
from the Slave. The following example details the transfer explained in
section 7.5.4 on page 47 of this
datasheet.
Master Reads from the Slave after setting data address in Slave (Write data address, READ Data)
S W A A A A SLAVE ADDRESS COMMAND BYTE High ADDR. BYTE Low ADDR. BYTE
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
From
Master
Start Bit
From
Master
S R A A A N P 8 BITS of DATA SLAVE ADDRESS 8 BITS of DATA 8 BITS of DATA
R/W
From
Master
Start Bit
From
Master
Stop Bit
From
Master
acknowledgement
from slave
acknowledgement
from Master
not-acknowled
from Master
acknowledgement
from Master
From Master
From Slave From Slave From Slave