Rainbow Electronics MAX16066 - Manual (Page 14)

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
MAX16065/MAX16066
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sequence delay is then counted before moving to the
next slot.
Slot 0 does not monitor any MON_ input and does not
control any EN_OUT_. Slot 0 waits for the Software
Enable bit r73h[0] to be a logic-high and for the voltage
on EN to rise above 1.4V before initiating the power-up
sequence and counting its own sequence delay.
Any MON_ input that suffers a fault that occurs during
power-up sequencing causes all the EN_OUT_s to turn
off and the sequencer to shut down regardless of the
state of the critical fault enables (see the Faults section
for more information). If a MON_ input is less critical to
system operation, it can be configured as “monitoring
only” (see Table 6) for either the primary or secondary
sequence. Monitoring for MON_ inputs assigned as
“monitoring only” begins after sequencing is complete
for that group, and can trigger a critical fault only if
specifically configured to do so using the critical fault
enables.
Power-Up
On power-up, when EN is high and the Software Enable
bit is 1, the MAX16065/MAX16066 begin sequencing
with Slot 0. After the sequencing delay for Slot 0 expires,
the sequencer advances to Slot 1, and all EN_OUT_s
assigned to the slot assert. All MON_ inputs assigned to
Slot 1 are monitored and when the voltage rises above the
UV fault threshold, the sequence delay counter is started.
When the t FAULT counter expires before all MON_ inputs
assigned to the slot are above the fault UV threshold,
a fault asserts. EN_OUT_ outputs are disabled and the
MAX16065/MAX16066 return to the power-off state.
When the sequence delay expires, the MAX16065/
MAX16066 proceed to the next slot.
After the voltages on all MON_ inputs assigned to the
last slot exceed the UV fault threshold and the slot delay
expires, the MAX16065/MAX16066 start the reset time-
out counter. After the reset timeout, RESET deasserts.
r75h[4:1] sets the t
FAULT delay. See Table 7 for details.
Power-Down
Power-down starts when EN is pulled low or the Software
Enable bit is set to ‘0.’ Power down EN_OUT_s simul-
taneously or in reverse-sequence mode by setting the
Reverse Sequence bit (r75h[0]) appropriately.
Reverse-Sequence Mode
When the MAX16065/MAX16066 are fully powered up
(including secondary sequence group, if enabled) and
EN or the Software Enable bit is set to ‘0’, the EN_OUT_s
assigned to Slot 12 deassert, the MAX16065/MAX16066
wait for the Slot 12 sequence delay and then proceed to
the previous slot (Slot 11), and so on until the EN_OUT_s
assigned to Slot 1 turn off. When simultaneous power-
down is selected (r75h[0] set to ‘0’), all EN_OUT_s turn
off at the same time.
Table 4. Power-Up/Power-Down Slot Delays
CODE VALUE
0000 25Fs
0001 500Fs
0010 1ms
0011 2ms
0100 3ms
0101 4ms
0110 6ms
0111 8ms
1000 10ms
1001 12ms
1010 25ms
1011 100ms
1100 200ms
1101 400ms
1110 800ms
1111 1.6s