Rainbow Electronics MAX9860 - Manual (Page 32)

MAX9860
Power Management
The MAX9860 includes complete power management
control to minimize power usage. The DAC and both
ADCs can be independently enabled so that only the
required circuitry is active.
16-Bit Mono Audio Voice Codec
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Table 11. Power Management Register
REGISTER ADDRESS B7 B6 B5 B4 B3 B2 B1 B0
0x10 SHDN 0 0 0 DACEN 0 ADCLEN ADCREN
BITS FUNCTION
SHDN
Active-Low Software Shutdown
0 = MAX9860 is in full shutdown.
1 = MAX9860 is powered on.
When SHDN = 0. All register settings are preserved and the I 2 C interface remains active.
DACEN
DAC Enable
0 = DAC disabled.
1 = DAC enabled.
ADCLEN/ADCREN
ADC Left/Right Enable
0 = Left/right ADC enabled.
1 = Left/right ADC disabled.
The left ADC must be enabled when using the right ADC.
Revision Code
The MAX9860 includes a revision code to allow easy
identification of the device revision. The current revision
code is 0x40.
Table 12. Revision Code Register
ADDR B7 B6 B5 B4 B3 B2 B1 B0
0xFF REV
I 2 C Serial Interface
The MAX9860 features an I 2 C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facili-
tate communication between the MAX9860 and the
master at clock rates up to 400kHz. Figure 6 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9860 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
to the MAX9860 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9860 transmits the proper slave address fol-
lowed by a series of nine SCL pulses. The MAX9860
transmits data on SDA in sync with the master-generat-
ed SCL pulses. The master acknowledges receipt of
each byte of data. Each read sequence is framed by a
START or REPEATED START condition, a not acknowl-
edge, and a STOP condition. SDA operates as both an
input and an open-drain output. A pullup resistor, typi-
cally greater than 500
Ω, is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically greater
than 500
Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the single master has an open-
drain SCL output. Series resistors in line with SDA and
SCL are optional. Series resistors protect the digital
inputs of the MAX9860 from high voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
SMBus is a trademark of Intel Corp.