Max9877 – Rainbow Electronics MAX9877 User Manual

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MAX9877

SLAVE ADDRESS

DATA BYTE

ACKNOWLEDGE FROM MAX9877

R/W

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9877

Figure 9. Writing One Byte of Data to the MAX9877

SCL

START

CONDITION

SDA

CLOCK PULSE FOR

ACKNOWLEDGMENT

ACKNOWLEDGE

NOT ACKNOWLEDGE

Figure 8. Acknowledge

Low RF Susceptibility, Mono Audio

Subsystem with DirectDrive Headphone Amplifier

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Early STOP Conditions

The MAX9877 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.

Slave Address

The MAX9877 is preprogrammed with a slave address
of 1001101R/(W). The address is defined as the seven
most significant bits (MSBs) followed by the Read/Write
bit. Setting the Read/Write bit to 1 configures the
MAX9877 for read mode. Setting the Read/Write bit to 0
configures the MAX9877 for write mode. The address is
the first byte of information sent to the MAX9877 after
the START condition.

Acknowledge

The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9877 uses to handshake receipt each byte of data
when in write mode (see Figure 8). The MAX9877 pulls
down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer

occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication.

The master pulls down SDA during the ninth clock
cycle to acknowledge receipt of data when the
MAX9877 is in read mode. An acknowledge is sent by
the master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the MAX9877, followed
by a STOP condition.

Write Data Format

A write to the MAX9877 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a
STOP condition. Figure 9 illustrates the proper frame
format for writing one byte of data to the MAX9877.
Figure 10 illustrates the frame format for writing n-bytes
of data to the MAX9877.

The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9877.
The MAX9877 acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.