Rainbow Electronics T89C51RD2 - Manual (Page 55)

55 Rev. F - 15 February, 2001
T89C51RD2
Table 31. Program Lock bits of the SSB
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X:do not care
WARNING: Security level 2 and 3 should only be programmed after FLASH and code verification.
8.5. FLASH memory status
T89C51RD2 parts are delivered in standard with the ISP boot in the FLASH memory. After ISP or parallel
programming, the possible contents of the FLASH memory are summarized on the figure below:
Figure 19. FLASH memory possible contents
8.6. Boot process
Boot loader FLASH
When the user application programs its own FLASH memory, all of the low level details are handled by a code
that is permanently contained in a 1k byte “Boot FLASH” and is located in the last kilobyte of the FLASH memory
from FC00h to FFFFh (See Figure 20). A user program simply calls the common entry point in the Boot FLASH
with appropriate parameters to accomplish the desired operation. Boot FLASH operations include functions like:
Program Lock Bits Protection description
Security
level
LB0 LB1
1 U U No program lock features enabled.
2 P U
following commands are disabled:
- program byte
- program status byte and boot vector
- erase status byte and boot vector
3 X P
Same as 2 and following commands also disabled:
- read byte
- read status byte and boot vector
- blank check
- program SSB level2
0000h
Boot
Virgin
FC00h
Default
Boot Boot
Virgin
Boot
Virgin
After ISP
After parallel
programming After parallel
programming After parallel
programming
Application Application
Boot
Virgin
After ISP
or appli or appli or appli
Dedicated
ISP Dedicated
ISP