Texas Instruments VLYNQ Port User Manual
User's guide
Table of contents
Document Outline
- Table of Contents
- Preface
- 1 Introduction
- 2 Peripheral Architecture
- 2.1 Clock Control
- 2.2 Signal Descriptions
- 2.3 Pin Multiplexing
- 2.4 Protocol Description
- 2.5 VLYNQ Functional Description
- 2.6 Initialization
- 2.7 Auto-Negotiation
- 2.8 Serial Interface Width Configuration
- 2.9 Address Translation
- 2.10 Flow Control
- 2.11 Reset Considerations
- 2.12 Interrupt Support
- 2.13 DMA Event Support
- 2.14 Power Management
- 2.15 Emulation Considerations
- 3 VLYNQ Port Registers
- 3.1 Revision Register (REVID)
- 3.2 Control Register (CTRL)
- 3.3 Status Register (STAT)
- 3.4 Interrupt Priority Vector Status/Clear Register (INTPRI)
- 3.5 Interrupt Status/Clear Register (INTSTATCLR)
- 3.6 Interrupt Pending/Set Register (INTPENDSET)
- 3.7 Interrupt Pointer Register (INTPTR)
- 3.8 Transmit Address Map Register (XAM)
- 3.9 Receive Address Map Size 1 Register (RAMS1)
- 3.10 Receive Address Map Offset 1 Register (RAMO1)
- 3.11 Receive Address Map Size 2 Register (RAMS2)
- 3.12 Receive Address Map Offset 2 Register (RAMO2)
- 3.13 Receive Address Map Size 3 Register (RAMS3)
- 3.14 Receive Address Map Offset 3 Register (RAMO3)
- 3.15 Receive Address Map Size 4 Register (RAMS4)
- 3.16 Receive Address Map Offset 4 Register (RAMO4)
- 3.17 Chip Version Register (CHIPVER)
- 3.18 Auto Negotiation Register (AUTNGO)
- 4 Remote Configuration Registers
- Appendix A VLYNQ Protocol Specifications
- Appendix B Write/Read Performance
- Appendix C Revision History