Texas Instruments VLYNQ Port - Manual (Page 40)

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Appendix A VLYNQ Protocol Specifications
A.1 Special 8b/10b Code Groups
A.2 Supported Ordered Sets
Appendix A
VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allow for in-band
packet delineation and control. The following sections include general 8b/10b coding definitions and
their implementation.
Table A-1. Special 8b/10b Code Groups
Code Group Name Octet Value Octet Bits Current RD - Current RD +
K28.0 1C 0001 1100 001111 0100 110000 1011
K28.1 3C 0011 1100 001111 1001 110000 0110
K28.2 5C 0101 1100 001111 0101 110000 1010
K28.3 7C 0111 1100 001111 0011 110000 1100
K28.4 9C 1001 1100 001111 0010 110000 1101
K28.5 BC 1011 1100 001111 1010 110000 0101
K28.6 DC 1101 1100 001111 0110 110000 1001
K28.7 FC 1111 1100 001111 1000 110000 0111
K23.7 F7 1111 0111 111010 1000 000101 0111
K27.7 FB 1111 1011 110110 1000 001001 0111
K29.7 FD 1111 1101 101110 1000 010001 0111
K30.7 FE 1111 1110 011110 1000 100001 0111
Each VLYNQ module must support a limited number of ordered sets. Ordered sets provide for the
delineation of packets and synchronization between VLYNQ modules at opposite ends of the serial
connection. VLYNQ 2.0 and later versions do not require some of the following ordered sets.
Table A-2. Supported Ordered Sets
Code Ordered Set Encoding Octet Value
/I/ Idle /K28.5/ BC
/T/ End of Packet /K29.7/ FD
/M/ Byte Disable /K23.7/ F7
/P/ Flow Control Enable /K28.0/ IC
/C/ Flow Control Disable /K28.2/ 5C
/E/ Error Indication /K28.1/ 3C
/0/ Init0 /K28.4/ 9C
/I/ Init1 /K28.6/ DC
/L/ Link /K30.7/ FE
40 VLYNQ Protocol Specifications SPRUE36A – September 2007
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