Texas Instruments VLYNQ Port - Manual (Page 20)

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2.10 Flow Control
Peripheral Architecture
Example 1. Address Translation Example
The remote address 0x 0400 : 0154 (or 0x0000 0054) was translated to 0x 8200 : 0054 on the DM644x
(local) device in this example.
The translated address for packets received on the serial interface is determined as follows:
If (RX Packet Address < RX Address Map Size 1 Register) {
Translated Address = RX Packet Address +
RX Address Map Offset 1 Register
} else if (RX Packet Address < (RX Address Map Size 1 Register +
RX Address Map Size 2 Register)) {
Translated Address = RX Packet Address +
RX Address Map Offset 2 Register -
RX Address Map Size 1 Register
} else if (RX Packet Address < (RX Address Map Size 1 Register +
RX Address Map Size 2 Register +
RX Address Map Size 3 Register)) {
Translated Address = RX Packet Address +
RX Address Map Offset 3 Register -
RX Address Map Size 1 Register -
RX Address Map Size 2 Register
} else if (RX Packet Address < (RX Address Map Size 1 Register +
RX Address Map Size 2 Register +
RX Address Map Size 3 Register +
RX Address Map Size 4 Register)) {
Translated Address = RX Packet Address +
RX Address Map Offset 4 Register -
RX Address Map Size 1 Register -
RX Address Map Size 2 Register -
RX Address Map Size 3 Register
} else {
Translated Address = 0x0
}
The VLYNQ module includes flow control features. The VLYNQ module automatically generates flow
control enable requests, /P/, when the RX/inbound FIFOs (FIFO1 and FIFO2) resources are consumed.
The FIFOs can take up to 16 32-bit words.
The remote device will begin transmitting idles, /I/, starting on the first byte boundary following reception of
the request. When sufficient RX FIFO resources have been made available, a flow control disable request,
/C/, is transmitted to the remote device. In response, the remote device will resume transmission of data.
See
Appendix A .
VLYNQ Port 20 SPRUE36A – September 2007
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