Texas Instruments VLYNQ Port - Manual (Page 6)

List of Tables
1 VLYNQ Port Pins ........................................................................................................... 12
2 Serial Interface Width ...................................................................................................... 16
3 Address Translation Example (Single Mapped Region)
..............................................................
18
4 Address Translation Example (Single Mapped Region)
..............................................................
19
5 VLYNQ Register Address Space ......................................................................................... 25
6 VLYNQ Port Controller Registers ........................................................................................ 25
7 Revision Register (REVID) Field Descriptions
.........................................................................
26
8 Control Register (CTRL) Field Descriptions ............................................................................ 27
9 Status Register (STAT) Field Descriptions ............................................................................. 29
10 Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions ........................................ 31
11 Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions
..................................................
31
12 Interrupt Pending/Set Register (INTPENDSET) Field Descriptions ................................................. 32
13 Interrupt Pointer Register (INTPTR) Field Descriptions ............................................................... 32
14 Address Map Register (XAM) Field Descriptions ...................................................................... 33
15 Receive Address Map Size 1 Register (RAMS1) Field Descriptions
................................................
34
16 Receive Address Map Offset 1 Register (RAMO1) Field Descriptions .............................................. 34
17 Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................ 35
18 Receive Address Map Offset 2 Register (RAMO2) Field Descriptions
..............................................
35
19 Receive Address Map Size 3 Register (RAMS3) Field Descriptions
................................................
36
20 Receive Address Map Offset 3 Register (RAMO3) Field Descriptions .............................................. 36
21 Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................ 37
22 Receive Address Map Offset 4 Register (RAMO4) Field Descriptions
..............................................
37
23 Chip Version Register (CHIPVER) Field Descriptions ................................................................. 38
24 Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................ 38
25 VLYNQ Port Remote Controller Registers .............................................................................. 39
A-1 Special 8b/10b Code Groups
.............................................................................................
40
A-2 Supported Ordered Sets .................................................................................................. 40
A-3 Packet Format (10-bit Symbol Representation) Description .......................................................... 42
B-1 Scaling Factors ............................................................................................................. 46
B-2 Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)
....................................
46
B-3 Relative Performance with Various Latencies .......................................................................... 47
C-1 Document Revision History ............................................................................................... 48
6 List of Tables SPRUE36A – September 2007
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