Texas Instruments TMS320C6452 DSP - Manual (Page 9)

1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
1.3 Functional Block Diagram
User's Guide
SPRUF85 – October 2007
DSP DDR2 Memory Controller
This document describes the DDR2 memory controller in the device.
The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM
devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories
are not supported. The DDR2 memory controller SDRAM can be used for program and data storage.
The DDR2 memory controller supports the following features:
•
JESD79D-2A standard compliant DDR2 SDRAM
•
256 Mbyte memory space
•
Data bus width of 32 or 16 bits
•
CAS latencies: 2, 3, 4, and 5
•
Internal banks: 1, 2, 4, and 8
•
Burst length: 8
•
Burst type: sequential
•
1 CE signal
•
Page sizes: 256, 512, 1024, and 2048
•
SDRAM auto-initialization
•
Self-refresh mode
•
Prioritized refresh
•
Programmable refresh rate and backlog counter
•
Programmable timing parameters
The DDR2 memory controller is the main interface to external DDR2 memory (see Figure 1 ). Master
peripherals, such as the EDMA controller and the CPU can access the DDR2 memory controller through
the switched central resource (SCR). The DDR2 memory controller performs all memory-related
background tasks such as opening and closing banks, refreshes, and command arbitration.
SPRUF85 – October 2007 DSP DDR2 Memory Controller 9
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