Texas Instruments TMS320C6452 DSP - Manual (Page 3)

Contents
Preface ............................................................................................................................... 6
1 Introduction ................................................................................................................ 9
1.1 Purpose of the Peripheral ....................................................................................... 9
1.2 Features ........................................................................................................... 9
1.3 Functional Block Diagram
.......................................................................................
9
1.4 Industry Standard(s) Compliance Statement
...............................................................
10
2 Peripheral Architecture .............................................................................................. 11
2.1 Clock Control
....................................................................................................
11
2.2 Memory Map .................................................................................................... 11
2.3 Signal Descriptions ............................................................................................. 11
2.4 Protocol Description(s) ......................................................................................... 13
2.5 Memory Width and Byte Alignment
..........................................................................
18
2.6 Address Mapping
...............................................................................................
19
2.7 DDR2 Memory Controller Interface .......................................................................... 22
2.8 Refresh Scheduling ............................................................................................ 25
2.9 Self-Refresh Mode .............................................................................................. 26
2.10 Reset Considerations
..........................................................................................
26
2.11 DDR2 SDRAM Memory Initialization
.........................................................................
27
2.12 Interrupt Support ................................................................................................ 28
2.13 EDMA Event Support .......................................................................................... 28
2.14 Emulation Considerations ..................................................................................... 28
3 Using the DDR2 Memory Controller ............................................................................. 29
3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM ............................................. 29
3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
.............
33
4 DDR2 Memory Controller Registers ............................................................................. 36
4.1 Module ID and Revision Register (MIDR)
...................................................................
37
4.2 DDR2 Memory Controller Status Register (DMCSTAT)
...................................................
37
4.3 SDRAM Configuration Register (SDCFG) ................................................................... 38
4.4 SDRAM Refresh Control Register (SDRFC) ................................................................ 40
4.5 SDRAM Timing 1 Register (SDTIM1) ........................................................................ 41
4.6 SDRAM Timing 2 Register (SDTIM2)
........................................................................
43
4.7 Burst Priority Register (BPRIO)
...............................................................................
44
4.8 DDR2 Memory Controller Control Register (DMCCTL) ................................................... 45
SPRUF85 – October 2007 Table of Contents 3
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