Texas Instruments TMS320C6452 DSP - Manual (Page 40)

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4.4 SDRAM Refresh Control Register (SDRFC)
DDR2 Memory Controller Registers
The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to:
•
Enter and Exit the self-refresh state.
•
Meet the refresh requirement of the attached DDR2 device by programming the rate at which the
DDR2 memory controller issues autorefresh commands.
The SDRFC is shown in Figure 23 and described in Table 21 .
Figure 23. SDRAM Refresh Control Register (SDRFC)
31 30 29 16
SR Rsvd Reserved
R/W- R/W- R-0x0
0x0 0x0
15 0
REFRESH_RATE
R/W-0x753
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. SDRAM Refresh Control Register (SDRFC) Field Descriptions
Bit Field Value Description
31 SR Self-refresh bit. Writing a 1 to this bit will cause connected SDRAM devices to be place into Self
Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state.
0 Exit self-refresh mode.
1 Enter self-refresh mode.
30 Reserved Reserved. Writes to this register must keep this field at its default value.
29-16 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15-0 REFRESH_RATE Refresh rate bits. The value in this field is used to define the rate at which connected SDRAM
devices will be refreshed as follows: effect.
SDRAM refresh rate = DDR_CLK clock rate / REFRESH_RATE
Writing a value less than 0x0100 to this field will cause it to be loaded with 2 * T_RFC value from
the SDRAM Timing 1 Register.
40 DSP DDR2 Memory Controller SPRUF85 – October 2007
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