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1 module id and revision register (midr), 2 ddr2 memory controller status register (dmcstat), Midr) – Texas Instruments TMS320C6452 DSP User Manual

Page 37: Dmcstat), Descriptions, Section 4.1, Section 4.2

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4.1

Module ID and Revision Register (MIDR)

4.2

DDR2 Memory Controller Status Register (DMCSTAT)

DDR2 Memory Controller Registers

The Module ID and Revision register (MIDR) is shown in

Figure 20

and described in

Table 18

.

Figure 20. Module ID and Revision Register (MIDR)

31

30

29

16

Reserved

MOD_ID

R-0x0

R-0x0031

15

8

7

0

MJ_REV

MN_REV

R-0x03

R-0x0F

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. Module ID and Revision Register (MIDR) Field Descriptions

Bit

Field

Value

Description

31-30

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

29-16

MOD_ID

Module ID bits.

15-8

MJ_REV

Major revision.

7-0

MN_REV

Minor revision.

The DDR2 memory controller status register (DMCSTAT) is shown in

Figure 21

and described in

Table 19

.

Figure 21. DDR2 Memory Controller Status Register (DMCSTAT)

31

30

29

16

Rsvd

Rsvd

Reserved

R-0x0

R-0x1

R-0x0

15

3

2

1

0

Reserved

IFRDY

Reserved

R-0x0

R-0x0

R-0x0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions

Bit

Field

Value

Description

31

Reserved

0

Reserved. The value always should be written as 0. write of 1 results an error in functionality.

30

Reserved

1

Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.

29-3

Reserved

0

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

2

IFRDY

DDR2 memory controller interface logic ready bit. The interface logic controls the signals used to
communicate with DDR2 SDRAM devices. This bit displays the status of the interface logic.

0

Interface logic is not ready; either powered down, not ready, or not locked.

1

Interface logic is powered up, locked, and ready for operation.

1-0

Reserved

0

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SPRUF85 – October 2007

DSP DDR2 Memory Controller

37

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