Renesas SuperH SH7600 Series - Manual (Page 28)

22
Figure 2.3 [Window trace] Page
Note: When the [L-bus] or [I-bus] radio button is selected, the following bus cycles will be
traced.
L-bus: A bus cycle generated by the CPU is acquired. A bus cycle is also acquired when
the cache has been hit.
I-bus: A bus cycle generated by the CPU or DMA is acquired. A bus cycle is not acquired
when the cache has been hit. The address information acquired by the I-bus is 28 bits and
the upper 4 bits are displayed as ‘*’. The source cannot be displayed in the [Trace]
window.
When U-RAM is accessed from the P0 space, the I-bus must be selected, and when
accessed from the P2 space, the L-bus must be selected. When a cache fill cycle is
acquired, I-bus must be selected.