Renesas SuperH SH7600 Series - Manual (Page 23)

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Table 2.4 Types of Break Conditions
Break Condition Type Description
Address bus condition (Address) Breaks when the SH7630 address bus value or the program
counter value matches the specified value.
Data bus condition (Data) Breaks when the SH7630 data bus value matches the
specified value. Byte, word, or longword can be specified as
the access data size.
Bus state condition
(Bus State) There are two bus state condition settings:
Read/Write condition: Breaks when the SH7630 RD or
RDWR signal level matches the specified condition.
Bus state condition: Breaks when the operating state in an
SH7630 bus cycle matches the specified condition.
Types of buses that can be specified are listed below.
•
L-bus (CPU-ALL): Indicates an instruction fetch and data
access, including a hit to the cache memory.
•
L-bus (CPU-Data): Indicates a data access by the CPU,
including a hit to the cache memory.
•
I-bus (CPU.DMA): Indicates a CPU cycle when the
cache memory is not hit, and a data access by the
DMA.
Internal I/O break condition Breaks when the SH7630 accesses the internal I/O.
Count Breaks when the conditions set are satisfied the specified
number of times.
Note: When U-RAM is accessed from the P0 space, the I-bus must be selected, and when
accessed from the P2 space, the L-bus must be selected. When cache fill cycle is acquired,
the I-bus must be selected.