Philips SC28L91 User Manual

Page 9

Philips Semiconductors

Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)

2004 Oct 21

PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA



)

ББББ

ББ

ББББ

Symbol

БББ

Pin
type

БББББББББББББББББББББББББББББ

БББББББББББББББББББББББББББ

БББББББББББББББББББББББББББББ

Name and function

ББББ

I/M

БББ

БББББББББББББББББББББББББББББ

Bus Configuration: When low configures the bus interface to the Conditions shown in this table.

ББББ

D0–D7

БББ

I/O

БББББББББББББББББББББББББББББ

Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the
CPU. D0 is the least significant bit.

ББББ

ББ

ББББ

CEN

БББ

БББББББББББББББББББББББББББББ

БББББББББББББББББББББББББББ

БББББББББББББББББББББББББББББ

Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on
D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.

ББББ

R/WN

БББ

БББББББББББББББББББББББББББББ

Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle.

ББББ

IACKN

БББ

БББББББББББББББББББББББББББББ

Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in
response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.

ББББ

ББ

ББББ

DACKN

БББ

БББББББББББББББББББББББББББББ

БББББББББББББББББББББББББББ

БББББББББББББББББББББББББББББ

Data Transfer Acknowledge: A3-State active-low output asserted in a write, read, or interrupt acknowledge cycle to
indicate proper transfer of data between the CPU and the UART.

ББББ

A0–A3

БББ

БББББББББББББББББББББББББББББ

Address Inputs: Select the UART internal registers and ports for read/write operations.

ББББ

ББ

ББББ

RESETN

БББ

БББББББББББББББББББББББББББББ

БББББББББББББББББББББББББББ

БББББББББББББББББББББББББББББ

Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,
stops the counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets
MR pointer to MR1. See Figure 4

ББББ

INTRN

БББ

БББББББББББББББББББББББББББББ

Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true. This pin requires a pullup.

ББББ

ББ

ББББ

X1/CLK

БББ

БББББББББББББББББББББББББББББ

БББББББББББББББББББББББББББ

БББББББББББББББББББББББББББББ

Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When
a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

ББББ

БББ

БББББББББББББББББББББББББББББ

Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this
pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

ББББ

RxD

БББ

БББББББББББББББББББББББББББББ

Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.

ББББ

ББ

ББББ

TxD

БББ

БББББББББББББББББББББББББББББ

БББББББББББББББББББББББББББ

БББББББББББББББББББББББББББББ

Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition
when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.

ББББ

OP0

БББ

БББББББББББББББББББББББББББББ

Output 0: General purpose output or request to send (RTSAN, active-Low). Can be deactivated automatically on
receive or transmit.

ББББ

OP1

БББ

БББББББББББББББББББББББББББББ

Output 1: General-purpose output.

ББББ

OP2

БББ

БББББББББББББББББББББББББББББ

Output 2: General purpose output or transmitter 1X or 16X clock output, or receiver 1X clock output.

ББББ

OP3

БББ

БББББББББББББББББББББББББББББ

Output 3: General purpose output.

ББББ

OP4

БББ

БББББББББББББББББББББББББББББ

Output 4: General purpose output or open-drain, active-Low, RxA interrupt ISR [1] output. DMA Control

ББББ

OP5

БББ

БББББББББББББББББББББББББББББ

Output 5: General-purpose output.

ББББ

OP6

ÁÁÁ

БББББББББББББББББББББББББББББ

Output 6: General purpose output or open-drain, active-Low, TxA interrupt ISR[0] output. DMA Control

ББББ

OP7

БББ

БББББББББББББББББББББББББББББ

Output 7: General-purpose output.

ББББ

IP0

БББ

БББББББББББББББББББББББББББББ

Input 0: General purpose input or clear to send active-Low input (CTSAN). Has Change of State Dector.

ББББ

IP1

БББ

БББББББББББББББББББББББББББББ

Input 1: General purpose input. Has Change of State Dector.

ББББ

IP2

БББ

БББББББББББББББББББББББББББББ

Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.

ББББ

IP3

БББ

БББББББББББББББББББББББББББББ

Input 3: General purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

ББББ

ББ

ББББ

IP4

БББ

БББББББББББББББББББББББББББББ

БББББББББББББББББББББББББББ

БББББББББББББББББББББББББББББ

Input 4: General purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

the received data is sampled on the rising edge of the clock.

ББББ

IP5

БББ

БББББББББББББББББББББББББББББ

Input 5: General purpose input.

ББББ

БББ

Pwr

БББББББББББББББББББББББББББББ

Power Supply: +3.3 or +5V supply input

10%

ББББ

GND

БББ

Pwr

БББББББББББББББББББББББББББББ

Ground