Philips SC28L91 User Manual

Page 28

Philips Semiconductors

Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)

2004 Oct 21

SR Status Register

Addr

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RECEIVED
BREAK

FRAMING
ERROR

PARITY
ERROR

OVERRUN
ERROR

TxEMT

TxRDY

FFULL

RxRDY

0x01

0 = No
1 = Yes

1. These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits [7:5] from

the top of the FIFO together with bits [4:0]. These bits are cleared by a “reset error status” command. In character mode they are discarded
when the corresponding data character is read from the FIFO. In block error mode, the error–reset command (command 4x or receiver
reset) must used to clear block error conditions.

SR[7]— Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received: further entries to the
FIFO are inhibited until the RxD line returns to the marking state for
at least one-half a bit time two successive edges of the internal or
external 1X clock. This will usually require a high time of one X1
clock period or 3 X1 edges since the clock of the controller is
not synchronous to the X1 clock.

When this bit is set, the ‘change in break’ bit in the ISR (ISR[2]) is
set. ISR[2] is also set when the end of the break condition, as
defined above, is detected.

The break detect circuitry can detect breaks that originate in the
middle of a received character. However, if a break begins in the
middle of a character, it must persist until at least the end of the next
character time in order for it to be detected.

This bit is reset by command 4 (0100) written to the command
register or by receiver reset.

SR[6]— Framing Error
This bit, when set, indicates that a stop bit was not detected (not a
logical 1) when the corresponding data character in the FIFO was

received. The stop bit check is made in the middle of the first stop bit

position.

SR[5]— Parity Error
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity.

In the special multi-drop mode the parity error bit stores the receive
A/D (Address/Data) bit.

SR[4]— Overrun Error
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost.

This bit is cleared by a ‘reset error status’ command.

SR[3]— Transmitter Empty (TxEMT)
This bit will be set when the transmitter under runs, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when
the transmitter is first enabled and at any time it is re-enabled after
either (a) reset, or (b) the transmitter has assumed the disabled
state. It is always set after transmission of the last stop bit of a
character if no character is in the THR awaiting transmission.

It is reset when the THR is loaded by the CPU, a pending
transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the under run condition.

SR[2]— Transmitter Ready (TxRDY)
This bit, when set, indicates that the transmit FIFO is not full and
ready to be loaded with another character. This bit is cleared when
the transmit FIFO is loaded by the CPU and there are (after this
load) no more empty locations in the FIFO. It is set when a
character is transferred to the transmit shift register. TxRDY is reset
when the transmitter is disabled and is set when the transmitter is
first enabled. Characters loaded to the TxFIFO while this bit is 0 will
be lost. This bit has different meaning from ISR[0].

SR[1]— FIFO Full (FFULL)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all eight (or 16) FIFO positions are occupied. It is

reset when the CPU reads the receive FIFO. If a character is waiting

in the receive shift register because the FIFO is full, FFULL will not
be reset when the CPU reads the receive FIFO. This bit has
different meaning from IRS when MR1 6 is programmed to a ‘1’.

SR[0]— Receiver Ready (RxRDY)
This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the FIFO and reset
when the CPU reads the receive FIFO, only if (after this read) there
are no more characters in the FIFO – the Rx FIFO becomes empty.