SMSC LAN9312 - Manual (Page 9)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 9 Revision 1.4 (08-19-08)
DATASHEET
14.4.2 Port 1 & 2 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
14.4.2.1 Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) ................................................................................................................ 287
14.4.2.2 Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ..................................................................................................................... 289
14.4.2.3 Port x PHY Identification MSB Register (PHY_ID_MSB_x).......................................................................................................................... 291
14.4.2.4 Port x PHY Identification LSB Register (PHY_ID_LSB_x)............................................................................................................................ 292
14.4.2.5 Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) ................................................................................................... 293
14.4.2.6 Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) ................................................. 296
14.4.2.7 Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) ......................................................................................................... 298
14.4.2.8 Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)..................................................................................... 299
14.4.2.9 Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) .............................................................................................................. 300
14.4.2.10 Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) .......................................................... 302
14.4.2.11 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)........................................................................................... 304
14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) ............................................................................................................ 305
14.4.2.13 Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x).............................................................................. 306
14.5 Switch Fabric Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
14.5.1 General Switch CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
14.5.1.1 Switch Device ID Register (SW_DEV_ID) .................................................................................................................................................... 318
14.5.1.2 Switch Reset Register (SW_RESET) ........................................................................................................................................................... 319
14.5.1.3 Switch Global Interrupt Mask Register (SW_IMR)........................................................................................................................................ 320
14.5.1.4 Switch Global Interrupt Pending Register (SW_IPR).................................................................................................................................... 321
14.5.2 Switch Port 0, Port 1, and Port 2 CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
14.5.2.1 Port x MAC Version ID Register (MAC_VER_ID_x) ..................................................................................................................................... 322
14.5.2.2 Port x MAC Receive Configuration Register (MAC_RX_CFG_x) ................................................................................................................. 323
14.5.2.3 Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) ........................................................................................... 324
14.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x).......................................................................................................... 325
14.5.2.5 Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)................................................................................ 326
14.5.2.6 Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)............................................................................ 327
14.5.2.7 Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)............................................................................ 328
14.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)........................................................................ 329
14.5.2.9 Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x) ..................................................................... 330
14.5.2.10 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) ............................................................................................. 331
14.5.2.11 Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)......................................................................................................... 332
14.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x).......................................................................................... 333
14.5.2.13 Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x) ............................................................................................. 334
14.5.2.14 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) ........................................................................................... 335
14.5.2.15 Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x) ........................................................................................ 336
14.5.2.16 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)........................................................................................ 337
14.5.2.17 Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x) ............................................................................................. 338
14.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) ...................................................................................... 339
14.5.2.19 Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x) ..................................................................................... 340
14.5.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) ................................................................ 341
14.5.2.21 Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x) ...................................................................................... 342
14.5.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) .................................................................................... 343
14.5.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) ................................................................................................................ 344
14.5.2.24 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) .................................................................................. 345
14.5.2.25 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) ............................................................................................... 346
14.5.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) ................................................................................................... 347
14.5.2.27 Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x) ........................................................................................................ 348
14.5.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) ......................................................................................................... 349
14.5.2.29 Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x) ............................................................................... 350
14.5.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) ........................................................................... 351
14.5.2.31 Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x) ........................................................................... 352
14.5.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) ....................................................................... 353
14.5.2.33 Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)..................................................................... 354
14.5.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) .......................................................................................... 355
14.5.2.35 Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) .................................................................................... 356
14.5.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) .......................................................................................... 357
14.5.2.37 Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x) ............................................................................................ 358
14.5.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) ................................................................................... 359
14.5.2.39 Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)............................................................................ 360
14.5.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) ............................................................................. 361
14.5.2.41 Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x) ............................................................................ 362
14.5.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)................................................................................ 363
14.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x) ..................................................................................................................................... 364
14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x) ................................................................................................................................. 365
14.5.3 Switch Engine CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
14.5.3.1 Switch Engine ALR Command Register (SWE_ALR_CMD) ........................................................................................................................ 366
14.5.3.2 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) .......................................................................................................... 367
14.5.3.3 Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) .......................................................................................................... 368
14.5.3.4 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)........................................................................................................... 370
14.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)........................................................................................................... 371
14.5.3.6 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) .................................................................................................... 373
14.5.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG) .................................................................................................................... 374
14.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD).................................................................................................................... 375
14.5.3.9 Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA).......................................................................................................... 376
14.5.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) .......................................................................................................... 377
14.5.3.11 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) ............................................................................................... 378
14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)................................................................................. 379
14.5.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) ...................................................................... 380
14.5.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) ....................................................................... 381