SMSC LAN9312 - Manual (Page 312)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 312 SMSC LAN9312
DATASHEET
0C10h MAC_RX_UNDSZE_CNT_2 Port 2 MAC Receive Undersize Count Register,
Section 14.5.2.3
0C11h MAC_RX_64_CNT_2 Port 2 MAC Receive 64 Byte Count Register, Section 14.5.2.4
0C12h MAC_RX_65_TO_127_CNT_2 Port 2 MAC Receive 65 to 127 Byte Count Register,
Section 14.5.2.5
0C13h MAC_RX_128_TO_255_CNT_2 Port 2 MAC Receive 128 to 255 Byte Count Register,
Section 14.5.2.6
0C14h MAC_RX_256_TO_511_CNT_2 Port 2 MAC Receive 256 to 511 Byte Count Register,
Section 14.5.2.7
0C15h MAC_RX_512_TO_1023_CNT_2 Port 2 MAC Receive 512 to 1023 Byte Count Register,
Section 14.5.2.8
0C16h MAC_RX_1024_TO_MAX_CNT_2 Port 2 MAC Receive 1024 to Max Byte Count Register,
Section 14.5.2.9
0C17h MAC_RX_OVRSZE_CNT_2 Port 2 MAC Receive Oversize Count Register,
Section 14.5.2.10
0C18h MAC_RX_PKTOK_CNT_2 Port 2 MAC Receive OK Count Register, Section 14.5.2.11
0C19h MAC_RX_CRCERR_CNT_2 Port 2 MAC Receive CRC Error Count Register,
Section 14.5.2.12
0C1Ah MAC_RX_MULCST_CNT_2 Port 2 MAC Receive Multicast Count Register,
Section 14.5.2.13
0C1Bh MAC_RX_BRDCST_CNT_2 Port 2 MAC Receive Broadcast Count Register,
Section 14.5.2.14
0C1Ch MAC_RX_PAUSE_CNT_2 Port 2 MAC Receive Pause Frame Count Register,
Section 14.5.2.15
0C1Dh MAC_RX_FRAG_CNT_2 Port 2 MAC Receive Fragment Error Count Register,
Section 14.5.2.16
0C1Eh MAC_RX_JABB_CNT_2 Port 2 MAC Receive Jabber Error Count Register,
Section 14.5.2.17
0C1Fh MAC_RX_ALIGN_CNT_2 Port 2 MAC Receive Alignment Error Count Register,
Section 14.5.2.18
0C20h MAC_RX_PKTLEN_CNT_2 Port 2 MAC Receive Packet Length Count Register,
Section 14.5.2.19
0C21h MAC_RX_GOODPKTLEN_CNT_2 Port 2 MAC Receive Good Packet Length Count Register,
Section 14.5.2.20
0C22h MAC_RX_SYMBL_CNT_2 Port 2 MAC Receive Symbol Error Count Register,
Section 14.5.2.21
0C23h MAC_RX_CTLFRM_CNT_2 Port 2 MAC Receive Control Frame Count Register,
Section 14.5.2.22
0C24 h -0C3F h RESERVED Reserved for Future Use
0C40h MAC_TX_CFG_2 Port 2 MAC Transmit Configuration Register, Section 14.5.2.23
0C41h MAC_TX_FC_SETTINGS_2 Port 2 MAC Transmit Flow Control Settings Register,
Section 14.5.2.24
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
REGISTER # SYMBOL REGISTER NAME